diff --git a/tcl/target/nrf51.cfg b/tcl/target/nrf51.cfg
index abb46fdda..129060d35 100644
--- a/tcl/target/nrf51.cfg
+++ b/tcl/target/nrf51.cfg
@@ -50,3 +50,11 @@ flash bank $_CHIPNAME.uicr nrf51 0x10001000 0 1 1 $_TARGETNAME
 #  clock to 1Mhz should be OK
 #
 adapter_khz 1000
+
+proc enable_all_ram {} {
+	# nRF51822 Product Anomaly Notice (PAN) #16 explains that not all RAM banks
+	# are reliably enabled after reset on some revisions (contrary to spec.) So after
+	# resetting we enable all banks via the RAMON register
+	mww 0x40000524 0xF
+}
+$_TARGETNAME configure -event reset-end {  enable_all_ram }