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git://git.code.sf.net/p/openocd/code
synced 2025-08-16 18:57:55 +10:00
openocd: drop iteration downsampling for keep_alive()
The function keep_alive() is optimized and return immediately if has nothing to do. There is no need to overly-complicate the code with extra counters or time computation plus the relative checks to reduce the number of calls to keep_alive(). Drop such extra code. Change-Id: I4574a3f154b5779f44105936c74af8fca1d2c49c Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: https://review.openocd.org/c/openocd/+/9064 Reviewed-by: Tomas Vanek <vanekt@fbl.cz> Tested-by: jenkins Reviewed-by: Lucien Buchmann <lucien.buchmann@dufour.aero>
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@ -112,10 +112,10 @@ static int cc26xx_wait_algo_done(struct flash_bank *bank, uint32_t params_addr)
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return retval;
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elapsed_ms = timeval_ms() - start_ms;
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if (elapsed_ms > 500)
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keep_alive();
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if (elapsed_ms > FLASH_TIMEOUT)
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break;
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keep_alive();
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};
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if (status != CC26XX_BUFFER_EMPTY) {
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@ -321,8 +321,6 @@ static int cc26xx_write(struct flash_bank *bank, const uint8_t *buffer,
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struct cc26xx_bank *cc26xx_bank = bank->driver_priv;
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struct cc26xx_algo_params algo_params[2];
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uint32_t size = 0;
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long long start_ms;
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long long elapsed_ms;
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uint32_t address;
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uint32_t index;
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@ -343,7 +341,6 @@ static int cc26xx_write(struct flash_bank *bank, const uint8_t *buffer,
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/* Write requested data, ping-ponging between two buffers */
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index = 0;
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start_ms = timeval_ms();
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address = bank->base + offset;
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while (count > 0) {
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@ -381,9 +378,7 @@ static int cc26xx_write(struct flash_bank *bank, const uint8_t *buffer,
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buffer += size;
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address += size;
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elapsed_ms = timeval_ms() - start_ms;
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if (elapsed_ms > 500)
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keep_alive();
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keep_alive();
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}
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/* If no error yet, wait for last buffer to finish */
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@ -65,10 +65,10 @@ static int cc3220sf_mass_erase(struct flash_bank *bank)
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done = true;
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} else {
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elapsed_ms = timeval_ms() - start_ms;
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if (elapsed_ms > 500)
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keep_alive();
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if (elapsed_ms > FLASH_TIMEOUT)
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break;
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keep_alive();
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}
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}
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@ -152,10 +152,10 @@ static int cc3220sf_erase(struct flash_bank *bank, unsigned int first,
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done = true;
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} else {
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elapsed_ms = timeval_ms() - start_ms;
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if (elapsed_ms > 500)
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keep_alive();
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if (elapsed_ms > FLASH_TIMEOUT)
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break;
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keep_alive();
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}
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}
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@ -219,10 +219,10 @@ static int msp432_wait_return_code(struct target *target)
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return retval;
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elapsed_ms = timeval_ms() - start_ms;
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if (elapsed_ms > 500)
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keep_alive();
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if (elapsed_ms > FLASH_TIMEOUT)
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break;
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keep_alive();
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};
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if (return_code != FLASH_SUCCESS) {
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@ -261,10 +261,10 @@ static int msp432_wait_inactive(struct target *target, uint32_t buffer)
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return retval;
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elapsed_ms = timeval_ms() - start_ms;
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if (elapsed_ms > 500)
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keep_alive();
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if (elapsed_ms > FLASH_TIMEOUT)
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break;
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keep_alive();
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};
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if (status_code != BUFFER_INACTIVE) {
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@ -678,8 +678,6 @@ static int msp432_write(struct flash_bank *bank, const uint8_t *buffer,
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struct msp432_algo_params algo_params;
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uint32_t size;
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uint32_t data_ready = BUFFER_DATA_READY;
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long long start_ms;
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long long elapsed_ms;
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bool is_info = bank->base == P4_FLASH_INFO_BASE;
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@ -753,7 +751,6 @@ static int msp432_write(struct flash_bank *bank, const uint8_t *buffer,
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}
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/* Write requested data, one buffer at a time */
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start_ms = timeval_ms();
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while (count > 0) {
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if (count > ALGO_BUFFER_SIZE)
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@ -786,9 +783,7 @@ static int msp432_write(struct flash_bank *bank, const uint8_t *buffer,
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count -= size;
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buffer += size;
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elapsed_ms = timeval_ms() - start_ms;
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if (elapsed_ms > 500)
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keep_alive();
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keep_alive();
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}
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/* Confirm that the flash helper algorithm is finished */
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@ -737,10 +737,10 @@ static int mspm0_fctl_wait_cmd_ok(struct flash_bank *bank)
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return retval;
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elapsed_ms = timeval_ms() - start_ms;
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if (elapsed_ms > 500)
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keep_alive();
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if (elapsed_ms > MSPM0_FLASH_TIMEOUT_MS)
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break;
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keep_alive();
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}
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if ((return_code & FCTL_STATCMD_CMDPASS_MASK) != FCTL_STATCMD_CMDPASS_STATPASS) {
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@ -2135,8 +2135,6 @@ int arm7_9_read_memory(struct target *target,
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reg[0] = address;
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arm7_9->write_core_regs(target, 0x1, reg);
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int j = 0;
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switch (size) {
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case 4:
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while (num_accesses < count) {
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@ -2166,8 +2164,7 @@ int arm7_9_read_memory(struct target *target,
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buffer += thisrun_accesses * 4;
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num_accesses += thisrun_accesses;
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if ((j++%1024) == 0)
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keep_alive();
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keep_alive();
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}
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break;
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case 2:
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@ -2199,8 +2196,7 @@ int arm7_9_read_memory(struct target *target,
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buffer += thisrun_accesses * 2;
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num_accesses += thisrun_accesses;
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if ((j++%1024) == 0)
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keep_alive();
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keep_alive();
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}
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break;
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case 1:
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@ -2231,8 +2227,7 @@ int arm7_9_read_memory(struct target *target,
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buffer += thisrun_accesses * 1;
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num_accesses += thisrun_accesses;
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if ((j++%1024) == 0)
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keep_alive();
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keep_alive();
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}
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break;
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}
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@ -151,9 +151,8 @@ int armv7a_l1_d_cache_inval_virt(struct target *target, uint32_t virt,
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struct armv7a_cache_common *armv7a_cache = &armv7a->armv7a_mmu.armv7a_cache;
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uint32_t linelen = armv7a_cache->dminline;
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uint32_t va_line, va_end;
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int retval, i = 0;
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retval = armv7a_l1_d_cache_sanity_check(target);
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int retval = armv7a_l1_d_cache_sanity_check(target);
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if (retval != ERROR_OK)
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return retval;
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@ -185,8 +184,7 @@ int armv7a_l1_d_cache_inval_virt(struct target *target, uint32_t virt,
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}
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while (va_line < va_end) {
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if ((i++ & 0x3f) == 0)
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keep_alive();
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keep_alive();
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/* DCIMVAC - Invalidate data cache line by VA to PoC. */
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retval = dpm->instr_write_data_r0(dpm,
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ARMV4_5_MCR(15, 0, 0, 7, 6, 1), va_line);
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@ -215,9 +213,8 @@ int armv7a_l1_d_cache_clean_virt(struct target *target, uint32_t virt,
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struct armv7a_cache_common *armv7a_cache = &armv7a->armv7a_mmu.armv7a_cache;
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uint32_t linelen = armv7a_cache->dminline;
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uint32_t va_line, va_end;
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int retval, i = 0;
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retval = armv7a_l1_d_cache_sanity_check(target);
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int retval = armv7a_l1_d_cache_sanity_check(target);
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if (retval != ERROR_OK)
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return retval;
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@ -229,8 +226,7 @@ int armv7a_l1_d_cache_clean_virt(struct target *target, uint32_t virt,
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va_end = virt + size;
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while (va_line < va_end) {
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if ((i++ & 0x3f) == 0)
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keep_alive();
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keep_alive();
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/* DCCMVAC - Data Cache Clean by MVA to PoC */
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retval = dpm->instr_write_data_r0(dpm,
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ARMV4_5_MCR(15, 0, 0, 7, 10, 1), va_line);
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@ -259,9 +255,8 @@ int armv7a_l1_d_cache_flush_virt(struct target *target, uint32_t virt,
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struct armv7a_cache_common *armv7a_cache = &armv7a->armv7a_mmu.armv7a_cache;
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uint32_t linelen = armv7a_cache->dminline;
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uint32_t va_line, va_end;
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int retval, i = 0;
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retval = armv7a_l1_d_cache_sanity_check(target);
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int retval = armv7a_l1_d_cache_sanity_check(target);
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if (retval != ERROR_OK)
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return retval;
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@ -273,8 +268,7 @@ int armv7a_l1_d_cache_flush_virt(struct target *target, uint32_t virt,
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va_end = virt + size;
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while (va_line < va_end) {
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if ((i++ & 0x3f) == 0)
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keep_alive();
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keep_alive();
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/* DCCIMVAC */
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retval = dpm->instr_write_data_r0(dpm,
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ARMV4_5_MCR(15, 0, 0, 7, 14, 1), va_line);
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@ -341,9 +335,8 @@ int armv7a_l1_i_cache_inval_virt(struct target *target, uint32_t virt,
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&armv7a->armv7a_mmu.armv7a_cache;
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uint32_t linelen = armv7a_cache->iminline;
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uint32_t va_line, va_end;
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int retval, i = 0;
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retval = armv7a_l1_i_cache_sanity_check(target);
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int retval = armv7a_l1_i_cache_sanity_check(target);
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if (retval != ERROR_OK)
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return retval;
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@ -355,8 +348,7 @@ int armv7a_l1_i_cache_inval_virt(struct target *target, uint32_t virt,
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va_end = virt + size;
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while (va_line < va_end) {
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if ((i++ & 0x3f) == 0)
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keep_alive();
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keep_alive();
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/* ICIMVAU - Invalidate instruction cache by VA to PoU. */
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retval = dpm->instr_write_data_r0(dpm,
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ARMV4_5_MCR(15, 0, 0, 7, 5, 1), va_line);
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@ -3216,8 +3216,6 @@ COMMAND_HANDLER(handle_wait_halt_command)
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/* wait for target state to change. The trick here is to have a low
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* latency for short waits and not to suck up all the CPU time
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* on longer waits.
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*
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* After 500ms, keep_alive() is invoked
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*/
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int target_wait_state(struct target *target, enum target_state state, unsigned int ms)
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{
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@ -3239,11 +3237,9 @@ int target_wait_state(struct target *target, enum target_state state, unsigned i
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nvp_value2name(nvp_target_state, state)->name);
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}
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if (cur - then > 500) {
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keep_alive();
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if (openocd_is_shutdown_pending())
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return ERROR_SERVER_INTERRUPTED;
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}
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keep_alive();
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if (openocd_is_shutdown_pending())
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return ERROR_SERVER_INTERRUPTED;
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if ((cur-then) > ms) {
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LOG_ERROR("timed out while waiting for target %s",
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