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git://git.code.sf.net/p/openocd/code
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498e559029
Add support for the Real-Time CPU (RCPU) of K1, which is a 32-bit RISC-V
N308 High-Efficiency Processor Core designed by Nuclei System Technology
Co. Ltd.
The JTAG interface can be configured to connect to either X60s or RCPU
processors. To enable JTAG for RCPU, set TARGET to "rcpu".
For example:
openocd -c "set TARGET rcpu" -f interface/cmsis-dap.cfg \
-f target/spacemit-k1.cfg
Change-Id: I9cd62fac332137afac17efa52702818de8f0b6f5
Signed-off-by: Junhui Liu <junhui.liu@pigmoral.tech>
Reviewed-on: https://review.openocd.org/c/openocd/+/8821
Reviewed-by: liangzhen <zhen.liang@spacemit.com>
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
95 lines
2.1 KiB
INI
95 lines
2.1 KiB
INI
# SPDX-License-Identifier: GPL-2.0-or-later
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#
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# SpacemiT Key Stone K1 target
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#
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# https://www.spacemit.com/key-stone-k1
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#
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transport select jtag
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adapter speed 2000
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# Set TARGET to "rcpu" to enable JTAG for RCPU
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if { [info exists TARGET] } {
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set _TARGET $TARGET
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} else {
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set _TARGET x60
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}
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if { $_TARGET == "rcpu" } {
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set CPUTAPID 0x10308A6D
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set DRVAL 0xe
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} else {
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set CPUTAPID 0x10000E21
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set DRVAL 0xa
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}
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if { [info exists CHIPNAME] } {
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set _CHIPNAME $CHIPNAME
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} else {
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set _CHIPNAME k1
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}
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if { [info exists CORES] } {
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set _cores $CORES
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} else {
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set _cores 1
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}
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if { [info exists SECJTAG] } {
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jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id $CPUTAPID
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} else {
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jtag newtap pre unknown -irlen 1 -expected-id 0x00000000 -disable
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jtag configure pre.unknown -event tap-enable ""
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jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id $CPUTAPID -disable
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jtag configure $_CHIPNAME.cpu -event tap-enable ""
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jtag newtap post unknown -irlen 9 -expected-id 0x08501C0D -ignore-version
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jtag configure post.unknown -event setup {
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global _CHIPNAME DRVAL
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irscan post.unknown 0x98
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drscan post.unknown 16 $DRVAL
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jtag tapenable pre.unknown
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jtag tapenable $_CHIPNAME.cpu
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}
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}
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set _TARGETNAME $_CHIPNAME.cpu_$_TARGET
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if { $_TARGET == "rcpu" } {
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target create $_TARGETNAME.0 riscv -chain-position $_CHIPNAME.cpu
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} else {
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set DBGBASE {0x0 0x400}
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set _smp_command "target smp"
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for { set _core 0 } { $_core < $_cores } { incr _core } {
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target create $_TARGETNAME.$_core riscv -chain-position $_CHIPNAME.cpu \
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-coreid [expr {$_core % 4}] -dbgbase [lindex $DBGBASE [expr {$_core / 4}]]
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if { [expr {$_core % 4}] == 0 } {
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$_TARGETNAME.$_core configure -rtos hwthread
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}
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set _smp_command "$_smp_command $_TARGETNAME.$_core"
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}
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eval $_smp_command
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}
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set _SPEED 8000
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$_TARGETNAME.0 configure -event examine-start {
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adapter speed $_SPEED
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puts [ adapter speed ]
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}
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foreach t [target names] {
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# $t riscv set_mem_access sysbus progbuf
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$t riscv set_mem_access progbuf
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}
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