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git://git.code.sf.net/p/openocd/code
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382148e4dd
With the old checkpatch we cannot use the correct format for the SPDX tags in the file .c, in fact the C99 comments are not allowed and we had to use the block comment. With the new checkpatch, let's switch to the correct SPDX format. Change created automatically through the command: sed -i \ 's,^/\* *\(SPDX-License-Identifier: .*[^ ]\) *\*/$,// \1,' \ $(find src/ contrib/ -name \*.c) Change-Id: I6da16506baa7af718947562505dd49606d124171 Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: https://review.openocd.org/c/openocd/+/7153 Tested-by: jenkins
372 lines
10 KiB
C
372 lines
10 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
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/***************************************************************************
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* Copyright (C) 2016 by Matthias Welwarsky *
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* matthias.welwarsky@sysgo.com *
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* *
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* Copyright (C) ST-Ericsson SA 2011 michel.jaouen@stericsson.com *
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***************************************************************************/
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#ifdef HAVE_CONFIG_H
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#include "config.h"
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#endif
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#include <helper/binarybuffer.h>
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#include <helper/command.h>
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#include "jtag/interface.h"
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#include "arm.h"
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#include "armv7a.h"
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#include "armv7a_mmu.h"
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#include "arm_opcodes.h"
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#include "cortex_a.h"
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#define SCTLR_BIT_AFE (1 << 29)
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/* V7 method VA TO PA */
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int armv7a_mmu_translate_va_pa(struct target *target, uint32_t va,
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target_addr_t *val, int meminfo)
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{
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int retval = ERROR_FAIL;
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struct armv7a_common *armv7a = target_to_armv7a(target);
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struct arm_dpm *dpm = armv7a->arm.dpm;
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uint32_t virt = va & ~0xfff, value;
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uint32_t NOS, NS, INNER, OUTER, SS;
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*val = 0xdeadbeef;
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retval = dpm->prepare(dpm);
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if (retval != ERROR_OK)
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goto done;
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/* mmu must be enable in order to get a correct translation
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* use VA to PA CP15 register for conversion */
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retval = dpm->instr_write_data_r0(dpm,
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ARMV4_5_MCR(15, 0, 0, 7, 8, 0),
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virt);
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if (retval != ERROR_OK)
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goto done;
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retval = dpm->instr_read_data_r0(dpm,
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ARMV4_5_MRC(15, 0, 0, 7, 4, 0),
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&value);
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if (retval != ERROR_OK)
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goto done;
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/* decode memory attribute */
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SS = (value >> 1) & 1;
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NOS = (value >> 10) & 1; /* Not Outer shareable */
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NS = (value >> 9) & 1; /* Non secure */
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INNER = (value >> 4) & 0x7;
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OUTER = (value >> 2) & 0x3;
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if (SS) {
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/* PAR[31:24] contains PA[31:24] */
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*val = value & 0xff000000;
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/* PAR [23:16] contains PA[39:32] */
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*val |= (target_addr_t)(value & 0x00ff0000) << 16;
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/* PA[23:12] is the same as VA[23:12] */
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*val |= (va & 0xffffff);
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} else {
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*val = (value & ~0xfff) + (va & 0xfff);
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}
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if (meminfo) {
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LOG_INFO("%" PRIx32 " : %" TARGET_PRIxADDR " %s outer shareable %s secured %s super section",
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va, *val,
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NOS == 1 ? "not" : " ",
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NS == 1 ? "not" : "",
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SS == 0 ? "not" : "");
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switch (OUTER) {
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case 0:
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LOG_INFO("outer: Non-Cacheable");
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break;
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case 1:
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LOG_INFO("outer: Write-Back, Write-Allocate");
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break;
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case 2:
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LOG_INFO("outer: Write-Through, No Write-Allocate");
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break;
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case 3:
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LOG_INFO("outer: Write-Back, no Write-Allocate");
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break;
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}
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switch (INNER) {
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case 0:
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LOG_INFO("inner: Non-Cacheable");
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break;
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case 1:
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LOG_INFO("inner: Strongly-ordered");
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break;
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case 3:
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LOG_INFO("inner: Device");
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break;
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case 5:
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LOG_INFO("inner: Write-Back, Write-Allocate");
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break;
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case 6:
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LOG_INFO("inner: Write-Through");
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break;
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case 7:
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LOG_INFO("inner: Write-Back, no Write-Allocate");
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break;
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default:
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LOG_INFO("inner: %" PRIx32 " ???", INNER);
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}
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}
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done:
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dpm->finish(dpm);
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return retval;
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}
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static const char *desc_bits_to_string(bool c_bit, bool b_bit, bool s_bit, bool ap2, int ap10, bool afe)
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{
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static char bits_string[64];
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unsigned int len;
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if (afe) {
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bool acc_r = true;
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bool acc_w = !ap2;
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bool priv = !(ap10 & 2);
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len = snprintf(bits_string, sizeof(bits_string), "%s%s%s access%s: %s%s",
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s_bit ? "S " : "", c_bit ? "C " : "", b_bit ? "B " : "",
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priv ? "(priv)" : "", acc_r ? "R" : "N", acc_w ? "W " : "O ");
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} else {
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bool priv_acc_w = !ap2;
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bool priv_acc_r = true;
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bool unpriv_acc_w = priv_acc_w;
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bool unpriv_acc_r = priv_acc_r;
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switch (ap10) {
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case 0:
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priv_acc_r = priv_acc_w = false;
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unpriv_acc_r = unpriv_acc_w = false;
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break;
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case 1:
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unpriv_acc_r = unpriv_acc_w = false;
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break;
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case 2:
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unpriv_acc_w = false;
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break;
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default:
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break;
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}
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len = snprintf(bits_string, sizeof(bits_string), "%s%s%s access(priv): %s%s access(unpriv): %s%s",
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s_bit ? "S " : "", c_bit ? "C " : "", b_bit ? "B " : "", priv_acc_r ? "R" : "N", priv_acc_w ? "W" : "O",
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unpriv_acc_r ? "R" : "N", unpriv_acc_w ? "W" : "O");
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}
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if (len >= sizeof(bits_string))
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bits_string[63] = 0;
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return bits_string;
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}
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static const char *l2_desc_bits_to_string(uint32_t l2_desc, bool afe)
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{
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bool c_bit = !!(l2_desc & (1 << 3));
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bool b_bit = !!(l2_desc & (1 << 2));
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bool s_bit = !!(l2_desc & (1 << 10));
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bool ap2 = !!(l2_desc & (1 << 9));
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int ap10 = (l2_desc >> 4) & 3;
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return desc_bits_to_string(c_bit, b_bit, s_bit, ap2, ap10, afe);
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}
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static const char *l1_desc_bits_to_string(uint32_t l1_desc, bool afe)
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{
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bool c_bit = !!(l1_desc & (1 << 3));
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bool b_bit = !!(l1_desc & (1 << 2));
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bool s_bit = !!(l1_desc & (1 << 16));
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bool ap2 = !!(l1_desc & (1 << 15));
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int ap10 = (l1_desc >> 10) & 3;
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return desc_bits_to_string(c_bit, b_bit, s_bit, ap2, ap10, afe);
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}
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COMMAND_HANDLER(armv7a_mmu_dump_table)
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{
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struct target *target = get_current_target(CMD_CTX);
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struct cortex_a_common *cortex_a = target_to_cortex_a(target);
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struct armv7a_common *armv7a = target_to_armv7a(target);
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struct armv7a_mmu_common *mmu = &armv7a->armv7a_mmu;
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struct armv7a_cache_common *cache = &mmu->armv7a_cache;
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uint32_t *first_lvl_ptbl;
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target_addr_t ttb;
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int ttbidx = 0;
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int retval;
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int pt_idx;
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int max_pt_idx = 4095;
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bool afe;
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if (CMD_ARGC < 1)
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return ERROR_COMMAND_SYNTAX_ERROR;
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if (!strcmp(CMD_ARGV[0], "addr")) {
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if (CMD_ARGC < 2)
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return ERROR_COMMAND_SYNTAX_ERROR;
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COMMAND_PARSE_NUMBER(target_addr, CMD_ARGV[1], ttb);
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if (CMD_ARGC > 2) {
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COMMAND_PARSE_NUMBER(int, CMD_ARGV[2], max_pt_idx);
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if (max_pt_idx < 1 || max_pt_idx > 4096)
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return ERROR_COMMAND_ARGUMENT_INVALID;
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max_pt_idx -= 1;
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}
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} else {
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if (mmu->cached != 1) {
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LOG_ERROR("TTB not cached!");
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return ERROR_FAIL;
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}
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COMMAND_PARSE_NUMBER(int, CMD_ARGV[0], ttbidx);
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if (ttbidx < 0 || ttbidx > 1)
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return ERROR_COMMAND_ARGUMENT_INVALID;
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ttb = mmu->ttbr[ttbidx] & mmu->ttbr_mask[ttbidx];
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if (ttbidx == 0) {
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int ttbcr_n = mmu->ttbcr & 0x7;
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max_pt_idx = 0x0fff >> ttbcr_n;
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}
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}
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LOG_USER("Page Directory at (phys): %8.8" TARGET_PRIxADDR, ttb);
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first_lvl_ptbl = malloc(sizeof(uint32_t)*(max_pt_idx+1));
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if (!first_lvl_ptbl)
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return ERROR_FAIL;
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/*
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* this may or may not be necessary depending on whether
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* the table walker is configured to use the cache or not.
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*/
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cache->flush_all_data_cache(target);
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retval = mmu->read_physical_memory(target, ttb, 4, max_pt_idx+1, (uint8_t *)first_lvl_ptbl);
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if (retval != ERROR_OK) {
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LOG_ERROR("Failed to read first-level page table!");
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return retval;
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}
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afe = !!(cortex_a->cp15_control_reg & SCTLR_BIT_AFE);
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for (pt_idx = 0; pt_idx <= max_pt_idx;) {
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uint32_t first_lvl_descriptor = target_buffer_get_u32(target,
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(uint8_t *)&first_lvl_ptbl[pt_idx]);
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LOG_DEBUG("L1 desc[%8.8x]: %8.8"PRIx32, pt_idx << 20, first_lvl_descriptor);
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/* skip empty entries in the first level table */
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if ((first_lvl_descriptor & 3) == 0) {
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pt_idx++;
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} else
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if ((first_lvl_descriptor & 0x40002) == 2) {
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/* section descriptor */
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uint32_t va_range = 1024*1024-1; /* 1MB range */
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uint32_t va_start = pt_idx << 20;
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uint32_t va_end = va_start + va_range;
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uint32_t pa_start = (first_lvl_descriptor & 0xfff00000);
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uint32_t pa_end = pa_start + va_range;
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LOG_USER("SECT: VA[%8.8"PRIx32" -- %8.8"PRIx32"]: PA[%8.8"PRIx32" -- %8.8"PRIx32"] %s",
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va_start, va_end, pa_start, pa_end, l1_desc_bits_to_string(first_lvl_descriptor, afe));
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pt_idx++;
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} else
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if ((first_lvl_descriptor & 0x40002) == 0x40002) {
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/* supersection descriptor */
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uint32_t va_range = 16*1024*1024-1; /* 16MB range */
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uint32_t va_start = pt_idx << 20;
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uint32_t va_end = va_start + va_range;
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uint32_t pa_start = (first_lvl_descriptor & 0xff000000);
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uint32_t pa_end = pa_start + va_range;
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LOG_USER("SSCT: VA[%8.8"PRIx32" -- %8.8"PRIx32"]: PA[%8.8"PRIx32" -- %8.8"PRIx32"] %s",
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va_start, va_end, pa_start, pa_end, l1_desc_bits_to_string(first_lvl_descriptor, afe));
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/* skip next 15 entries, they're duplicating the first entry */
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pt_idx += 16;
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} else {
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target_addr_t second_lvl_ptbl = first_lvl_descriptor & 0xfffffc00;
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uint32_t second_lvl_descriptor;
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uint32_t *pt2;
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int pt2_idx;
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/* page table, always 1KB long */
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pt2 = malloc(1024);
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retval = mmu->read_physical_memory(target, second_lvl_ptbl,
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4, 256, (uint8_t *)pt2);
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if (retval != ERROR_OK) {
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LOG_ERROR("Failed to read second-level page table!");
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return ERROR_FAIL;
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}
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for (pt2_idx = 0; pt2_idx < 256; ) {
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second_lvl_descriptor = target_buffer_get_u32(target,
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(uint8_t *)&pt2[pt2_idx]);
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if ((second_lvl_descriptor & 3) == 0) {
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/* skip entry */
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pt2_idx++;
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} else
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if ((second_lvl_descriptor & 3) == 1) {
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/* large page */
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uint32_t va_range = 64*1024-1; /* 64KB range */
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uint32_t va_start = (pt_idx << 20) + (pt2_idx << 12);
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uint32_t va_end = va_start + va_range;
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uint32_t pa_start = (second_lvl_descriptor & 0xffff0000);
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uint32_t pa_end = pa_start + va_range;
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LOG_USER("LPGE: VA[%8.8"PRIx32" -- %8.8"PRIx32"]: PA[%8.8"PRIx32" -- %8.8"PRIx32"] %s",
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va_start, va_end, pa_start, pa_end, l2_desc_bits_to_string(second_lvl_descriptor, afe));
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pt2_idx += 16;
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} else {
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/* small page */
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uint32_t va_range = 4*1024-1; /* 4KB range */
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uint32_t va_start = (pt_idx << 20) + (pt2_idx << 12);
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uint32_t va_end = va_start + va_range;
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uint32_t pa_start = (second_lvl_descriptor & 0xfffff000);
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uint32_t pa_end = pa_start + va_range;
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LOG_USER("SPGE: VA[%8.8"PRIx32" -- %8.8"PRIx32"]: PA[%8.8"PRIx32" -- %8.8"PRIx32"] %s",
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va_start, va_end, pa_start, pa_end, l2_desc_bits_to_string(second_lvl_descriptor, afe));
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pt2_idx++;
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}
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}
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free(pt2);
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pt_idx++;
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}
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}
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free(first_lvl_ptbl);
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return ERROR_OK;
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}
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static const struct command_registration armv7a_mmu_group_handlers[] = {
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{
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.name = "dump",
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.handler = armv7a_mmu_dump_table,
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.mode = COMMAND_ANY,
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.help = "dump translation table 0, 1 or from <address>",
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.usage = "(0|1|addr <address> [num_entries])",
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},
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COMMAND_REGISTRATION_DONE
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};
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const struct command_registration armv7a_mmu_command_handlers[] = {
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{
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.name = "mmu",
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.mode = COMMAND_ANY,
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.help = "mmu command group",
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.usage = "",
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.chain = armv7a_mmu_group_handlers,
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},
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COMMAND_REGISTRATION_DONE
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};
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