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11116ef6ad
In addition to the debug TAPs, the ICEPick C also supports a bank of Test TAPs (limited functionality intended for non-debuggable targets). Added support for Test TAPs to the icepick_c_tapenable routine. Port numbers of 0 to 15 will continue to be handled as a debug TAP number. Test TAPs will be port numbers of 16 to 31. This functionality will be needed for doing a flash mass erase on CC26xx/CC13xx targets. It is possible for user application to block even adding the Cortex M TAP to the scan chain, so the only way to unbrick the target and erase the flash is using a component on a test TAP of the device's ICEPick router. Change-Id: I0aa52a08d43a00cbd396efdeadd504fc31c98510 Signed-off-by: Edward Fewell <efewell@ti.com> Reviewed-on: http://openocd.zylin.com/5715 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com> |
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| .. | ||
| board | ||
| chip | ||
| cpld | ||
| cpu | ||
| fpga | ||
| interface | ||
| target | ||
| test | ||
| tools | ||
| bitsbytes.tcl | ||
| mem_helper.tcl | ||
| memory.tcl | ||
| mmr_helpers.tcl | ||