mirror of
git://git.code.sf.net/p/openocd/code
synced 2025-07-26 14:39:32 +10:00
a1bbf4b75b
It depends on the particular target whether it can work with SRST asserted or not, so this belongs to the target config rather than the board config. Also, this allows for simple openocd -f myboard.cfg -c "reset_config connect_assert_srst" command to be used whenever a user feels a need to connect to an unresponsive target. Change-Id: I3d8da9ae47088fc0c75a20bfdd20074be1014de0 Signed-off-by: Paul Fertser <fercerpav@gmail.com> Reviewed-on: http://openocd.zylin.com/2459 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
92 lines
2.3 KiB
INI
92 lines
2.3 KiB
INI
# script for stm32f4x family
|
|
|
|
#
|
|
# stm32 devices support both JTAG and SWD transports.
|
|
#
|
|
source [find target/swj-dp.tcl]
|
|
|
|
if { [info exists CHIPNAME] } {
|
|
set _CHIPNAME $CHIPNAME
|
|
} else {
|
|
set _CHIPNAME stm32f4x
|
|
}
|
|
|
|
set _ENDIAN little
|
|
|
|
# Work-area is a space in RAM used for flash programming
|
|
# By default use 64kB
|
|
if { [info exists WORKAREASIZE] } {
|
|
set _WORKAREASIZE $WORKAREASIZE
|
|
} else {
|
|
set _WORKAREASIZE 0x10000
|
|
}
|
|
|
|
#jtag scan chain
|
|
if { [info exists CPUTAPID] } {
|
|
set _CPUTAPID $CPUTAPID
|
|
} else {
|
|
if { [using_jtag] } {
|
|
# See STM Document RM0090
|
|
# Section 38.6.3 - corresponds to Cortex-M4 r0p1
|
|
set _CPUTAPID 0x4ba00477
|
|
} {
|
|
set _CPUTAPID 0x2ba01477
|
|
}
|
|
}
|
|
|
|
swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
|
|
|
|
if { [info exists BSTAPID] } {
|
|
set _BSTAPID $BSTAPID
|
|
} else {
|
|
# See STM Document RM0090
|
|
# Section 38.6.2
|
|
# STM32F405xx/07xx and STM32F415xx/17xx
|
|
set _BSTAPID1 0x06413041
|
|
# STM32F42xxx and STM32F43xxx
|
|
set _BSTAPID2 0x06419041
|
|
# See STM Document RM0368 (Rev. 3)
|
|
# STM32F401B/C
|
|
set _BSTAPID3 0x06423041
|
|
# STM32F401D/E
|
|
set _BSTAPID4 0x06433041
|
|
# See STM Document RM0383 (Rev 2)
|
|
# STM32F411
|
|
set _BSTAPID5 0x06431041
|
|
}
|
|
|
|
if {[using_jtag]} {
|
|
swj_newdap $_CHIPNAME bs -irlen 5 -expected-id $_BSTAPID1 \
|
|
-expected-id $_BSTAPID2 -expected-id $_BSTAPID3 \
|
|
-expected-id $_BSTAPID4 -expected-id $_BSTAPID5
|
|
}
|
|
|
|
set _TARGETNAME $_CHIPNAME.cpu
|
|
target create $_TARGETNAME cortex_m -endian $_ENDIAN -chain-position $_TARGETNAME
|
|
|
|
$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
|
|
|
|
set _FLASHNAME $_CHIPNAME.flash
|
|
flash bank $_FLASHNAME stm32f2x 0 0 0 0 $_TARGETNAME
|
|
|
|
# JTAG speed should be <= F_CPU/6. F_CPU after reset is 16MHz, so use F_JTAG = 2MHz
|
|
#
|
|
# Since we may be running of an RC oscilator, we crank down the speed a
|
|
# bit more to be on the safe side. Perhaps superstition, but if are
|
|
# running off a crystal, we can run closer to the limit. Note
|
|
# that there can be a pretty wide band where things are more or less stable.
|
|
adapter_khz 2000
|
|
|
|
adapter_nsrst_delay 100
|
|
if {[using_jtag]} {
|
|
jtag_ntrst_delay 100
|
|
}
|
|
|
|
reset_config srst_nogate
|
|
|
|
if {![using_hla]} {
|
|
# if srst is not fitted use SYSRESETREQ to
|
|
# perform a soft reset
|
|
cortex_m reset_config sysresetreq
|
|
}
|