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435e6101c6
With this commit we add tcl files which describes ARCv2 architecture features and configure files for ARCv2 EMSK board. Changes since v1: -Moved from http://openocd.zylin.com/#/c/5332/4 into separate commit. Changes: 22.01.2020: -Removed "actionpoints" handling code in tcl/cpu/arc/v2.tcl because this capability is not supported yet. Changes: 17.03.2020: -Update Licence headers -Cleanup indents -Removed "reset halt" in boards .tcl -Updated adapter frequency commands Changes: 15.03.2020: -Removed "init" in the of boards .tcl Change-Id: I51bf620abe7b8e046e1dccc861a7d963965d3a42 Signed-off-by: Evgeniy Didin <didin@synopsys.com> Cc: Alexey Brodkin <abrodkin@synopsys.com> Reviewed-on: http://openocd.zylin.com/5350 Tested-by: jenkins Reviewed-by: Oleksij Rempel <linux@rempel-privat.de>
41 lines
1.3 KiB
Tcl
41 lines
1.3 KiB
Tcl
# Copyright (C) 2015, 2020 Synopsys, Inc.
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# Anton Kolesov <anton.kolesov@synopsys.com>
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# Didin Evgeniy <didin@synopsys.com>
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#
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# SPDX-License-Identifier: GPL-2.0-or-later
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# Things common to all ARCs
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# It is assumed that target is already halted.
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proc arc_common_reset { {target ""} } {
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if { $target != "" } {
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targets $target
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}
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halt
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# 1. Interrupts are disabled (STATUS32.IE)
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# 2. The status register flags are cleared.
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# All fields, except the H bit, are set to 0 when the processor is Reset.
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arc jtag set-aux-reg 0xA 0x1
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# 3. The loop count, loop start, and loop end registers are cleared.
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arc jtag set-core-reg 60 0
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arc jtag set-aux-reg 0x2 0
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arc jtag set-aux-reg 0x3 0
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# Program execution begins at the address referenced by the four byte reset
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# vector located at the interrupt vector base address, which is the first
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# entry (offset 0x00) in the vector table.
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set int_vector_base [arc jtag get-aux-reg 0x25]
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set start_pc ""
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mem2array start_pc 32 $int_vector_base 1
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arc jtag set-aux-reg 0x6 $start_pc(0)
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# It is OK to do uncached writes - register cache will be invalidated by
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# the reset_assert() function.
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}
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# vim:expandtab:
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