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1e07f7bb6a
Change-Id: I68bd6b7c19d9d1bee13d0921c32b4490e68ab8f2 Signed-off-by: is2t <devel@is2t.com> Reviewed-on: http://openocd.zylin.com/1002 Tested-by: jenkins Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
21 lines
736 B
INI
21 lines
736 B
INI
# NXP LPC1788 Cortex-M3 with 512kB Flash and 64kB Local On-Chip SRAM,
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set CHIPNAME lpc1788
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set CPUTAPID 0x4ba00477
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set CPURAMSIZE 0x10000
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set CPUROMSIZE 0x80000
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# After reset the chip is clocked by the ~12MHz internal RC oscillator.
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# When board-specific code (reset-init handler or device firmware)
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# configures another oscillator and/or PLL0, set CCLK to match; if
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# you don't, then flash erase and write operations may misbehave.
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# (The ROM code doing those updates cares about core clock speed...)
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#
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# CCLK is the core clock frequency in KHz
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set CCLK 12000
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#Include the main configuration file.
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source [find target/lpc17xx.cfg];
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# if srst is not fitted, use SYSRESETREQ to perform a soft reset
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cortex_m3 reset_config sysresetreq
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