mirror of
git://git.code.sf.net/p/openocd/code
synced 2025-07-24 05:59:49 +10:00
60e24aa597
Startup now mostly works, except that the initial target state is "unknown" ... previously, it refused to even start. Getting that far required fixing the ircapture value (which can never have been correct!) and the default JTAG clock rate, then providing custom reset script. The "reset" command is still iffy. DCSR updates, and loading the debug handler, report numerous DR/IR capture failures. But once that's done, "poll" reports that the CPU is halted (which it shouldn't be, this was "reset run"!), due to the rather curious reason "target-not-halted". Summary: you still can't debug these parts, but it's closer. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
56 lines
1.2 KiB
INI
56 lines
1.2 KiB
INI
# PXA255 chip ... originally from Intel, PXA line was sold to Marvell.
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# This chip is now at end-of-life. Final orders have been taken.
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if { [info exists CHIPNAME] } {
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set _CHIPNAME $CHIPNAME
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} else {
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set _CHIPNAME pxa255
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}
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if { [info exists ENDIAN] } {
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set _ENDIAN $ENDIAN
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} else {
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set _ENDIAN little
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}
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if { [info exists CPUTAPID ] } {
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set _CPUTAPID $CPUTAPID
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} else {
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set _CPUTAPID 0x69264013
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}
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jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id $_CPUTAPID
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set _TARGETNAME $_CHIPNAME.cpu
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target create $_TARGETNAME xscale -endian $_ENDIAN \
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-chain-position $_CHIPNAME.cpu
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# PXA255 comes out of reset using 3.6864 MHz oscillator.
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# Until the PLL kicks in, keep the JTAG clock slow enough
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# that we get no errors.
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jtag_khz 300
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$_TARGETNAME configure -event "reset-start" { jtag_khz 300 }
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# reset processing that works with PXA
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proc init_reset {mode} {
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# assert both resets; equivalent to power-on reset
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jtag_reset 1 1
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# drop TRST after at least 32 cycles
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sleep 1
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jtag_reset 0 1
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# minimum 32 TCK cycles to wake up the controller
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runtest 50
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# now the TAP will be responsive; validate scanchain
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jtag arp_init
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# ... and take it out of reset
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jtag_reset 0 0
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}
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proc jtag_init {} {
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init_reset startup
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}
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