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git://git.code.sf.net/p/openocd/code
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f5657aa76e
Jimtcl commit 1843b79a03dd ("expr: TIP 526, only support a single
arg") drops the support for multi-argument syntax for the TCL
command 'expr'.
In the TCL scripts distributed with OpenOCD there are 1700+ lines
that should be modified before switching to jimtcl 0.81.
Apply the script below on every script in tcl folder. It fixes
more than 92% of the lines
%<---%<---%<---%<---%<---%<---%<---%<---%<---%<---%<---%<---%<---
#!/usr/bin/perl -Wpi
my $re_sym = qr{[a-z_][a-z0-9_]*}i;
my $re_var = qr{(?:\$|\$::)$re_sym};
my $re_const = qr{0x[0-9a-f]+|[0-9]+|[0-9]*\.[0-9]*}i;
my $re_item = qr{(?:~\s*)?(?:$re_var|$re_const)};
my $re_op = qr{<<|>>|[+\-*/&|]};
my $re_expr = qr{(
(?:\(\s*(?:$re_item|(?-1))\s*\)|$re_item)
\s*$re_op\s*
(?:$re_item|(?-1)|\(\s*(?:$re_item|(?-1))\s*\))
)}x;
# [expr [dict get $regsC100 SYM] + HEXNUM]
s/\[expr (\[dict get $re_var $re_sym\s*\] \+ *$re_const)\]/\[expr \{$1\}\]/;
# [ expr (EXPR) ]
# [ expr EXPR ]
# note: $re_expr captures '$3'
s/\[(\s*expr\s*)\((\s*$re_expr\s*)\)(\s*)\]/\[$1\{$2\}$4\]/;
s/\[(\s*expr\s*)($re_expr)(\s*)\]/\[$1\{$2\}$4\]/;
%<---%<---%<---%<---%<---%<---%<---%<---%<---%<---%<---%<---%<---
Change-Id: I0d6bddc6abf6dd29062f2b4e72b5a2b5080293b9
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/6159
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
59 lines
1.9 KiB
Tcl
59 lines
1.9 KiB
Tcl
# Copyright (C) 2015, 2020 Synopsys, Inc.
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# Anton Kolesov <anton.kolesov@synopsys.com>
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# Didin Evgeniy <didin@synopsys.com>
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#
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# SPDX-License-Identifier: GPL-2.0-or-later
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source [find cpu/arc/v2.tcl]
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proc arc_hs_examine_target { target } {
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# Will set current target for us.
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arc_v2_examine_target $target
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}
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proc arc_hs_init_regs { } {
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arc_v2_init_regs
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[target current] configure \
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-event examine-end "arc_hs_examine_target [target current]"
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}
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# Scripts in "target" folder should call this function instead of direct
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# invocation of arc_common_reset.
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proc arc_hs_reset { {target ""} } {
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arc_v2_reset $target
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# Invalidate L2 cache if there is one.
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set l2_config [$target arc jtag get-aux-reg 0x901]
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# Will return 0, if cache is not present and register doesn't exist.
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set l2_ctrl [$target arc jtag get-aux-reg 0x903]
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if { ($l2_config != 0) && (($l2_ctrl & 1) == 0) } {
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puts "L2 cache is present and not disabled"
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# Wait until BUSY bit is 0.
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puts "Invalidating L2 cache..."
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$target arc jtag set-aux-reg 0x905 1
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# Dummy read of SLC_AUX_CACHE_CTRL bit, as described in:
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# https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux-stable.git/commit/arch/arc?id=c70c473396cbdec1168a6eff60e13029c0916854
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set l2_ctrl [$target arc jtag get-aux-reg 0x903]
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set l2_ctrl [$target arc jtag get-aux-reg 0x903]
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while { ($l2_ctrl & 0x100) != 0 } {
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set l2_ctrl [$target arc jtag get-aux-reg 0x903]
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}
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# Flush cache if needed. If SLC_AUX_CACHE_CTRL.IM is 1, then invalidate
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# operation already flushed everything.
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if { ($l2_ctrl & 0x40) == 0 } {
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puts "Flushing L2 cache..."
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$target arc jtag set-aux-reg 0x904 1
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set l2_ctrl [$target arc jtag get-aux-reg 0x903]
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set l2_ctrl [$target arc jtag get-aux-reg 0x903]
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while { [expr {$l2_ctrl & 0x100}] != 0 } {
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set l2_ctrl [$target arc jtag get-aux-reg 0x903]
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}
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}
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puts "L2 cache has been flushed and invalidated."
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}
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}
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