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93a3a82e49
This add support to the Xilinx BSCAN_* virtual JTAG interface. This is the Xilinx equivalent of the Altera sld_virtual_jtag interface, it allows a user to connect to the debug unit through the main FPGA JTAG connection. Change-Id: Ia438e910650cff9cbc8f810b719fc1d5de5a8188 Signed-off-by: Sergio Chico <sergio.chico@gmail.com> Reviewed-on: http://openocd.zylin.com/1806 Tested-by: jenkins Reviewed-by: Franck Jullien <franck.jullien@gmail.com> Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
46 lines
1016 B
INI
46 lines
1016 B
INI
# If you want to use the VJTAG TAP or the XILINX BSCAN,
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# you must set your FPGA TAP ID here
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set FPGATAPID 0x020b30dd
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# Choose your TAP core (VJTAG , MOHOR or XILINX_BSCAN)
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set TAP_TYPE VJTAG
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# Set your chip name
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set CHIPNAME or1200
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source [find target/or1k.cfg]
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# Set the adapter speed
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adapter_khz 3000
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# Enable the target description feature
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gdb_target_description enable
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# Add a new register in the cpu register list. This register will be
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# included in the generated target descriptor file.
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# format is addreg [name] [address] [feature] [reg_group]
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addreg rtest 0x1234 org.gnu.gdb.or1k.group0 system
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# Override default init_reset
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proc init_reset {mode} {
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soft_reset_halt
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resume
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}
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# Target initialization
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init
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echo "Halting processor"
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halt
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foreach name [target names] {
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set y [$name cget -endian]
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set z [$name cget -type]
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puts [format "Chip is %s, Endian: %s, type: %s" \
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$name $y $z]
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}
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set c_blue "\033\[01;34m"
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set c_reset "\033\[0m"
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puts [format "%sTarget ready...%s" $c_blue $c_reset]
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