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Add support for OpenRISC target. This implementation supports the adv_debug_sys debug unit core. The mohor dbg_if is not supported. Support for mohor TAP core and Altera Virtual JTAG core are also provided. Change-Id: I3b1cfab1bbb28e497c4fca6ed1bd3a4362609b72 Signed-off-by: Franck Jullien <franck.jullien@gmail.com> Reviewed-on: http://openocd.zylin.com/1547 Tested-by: jenkins Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
54 lines
1.3 KiB
INI
54 lines
1.3 KiB
INI
set _ENDIAN big
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if { [info exists CHIPNAME] } {
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set _CHIPNAME $CHIPNAME
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} else {
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set _CHIPNAME or1k
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}
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if { [info exists TAP_TYPE] } {
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set _TAP_TYPE $TAP_TYPE
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} else {
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puts "You need to select a tap type"
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shutdown
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}
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# Configure the target
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if { [string compare $_TAP_TYPE "VJTAG"] == 0 } {
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if { [info exists FPGATAPID] } {
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set _FPGATAPID $FPGATAPID
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} else {
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puts "You need to set your FPGA JTAG ID"
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shutdown
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}
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jtag newtap $_CHIPNAME cpu -irlen 10 -expected-id $_FPGATAPID
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set _TARGETNAME $_CHIPNAME.cpu
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target create $_TARGETNAME or1k -endian $_ENDIAN -chain-position $_TARGETNAME
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# Select the TAP core we are using
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tap_select vjtag
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} else {
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# OpenCores Mohor JTAG TAP ID
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set _CPUTAPID 0x14951185
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jtag newtap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID
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set _TARGETNAME $_CHIPNAME.cpu
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target create $_TARGETNAME or1k -endian $_ENDIAN -chain-position $_TARGETNAME
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# Select the TAP core we are using
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tap_select mohor
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}
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# Select the debug unit core we are using. This debug unit as an option.
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proc ADBG_USE_HISPEED {} { return 1 }
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# If ADBG_USE_HISPEED is set (options bit 1), status bits will be skipped
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# on burst reads and writes to improve download speeds.
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# This option must match the RTL configured option.
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du_select adv [ADBG_USE_HISPEED]
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