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git://git.code.sf.net/p/openocd/code
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0c8ec7c826
It's Cortex-Xn, not Cortex Xn or cortex xn or cortex-xn or CORTEX-Xn or CortexXn. Further it's Cortex-M0+, not M0plus. Cf. http://www.arm.com/products/processors/index.php Consistently write it the official way, so that it stops propagating. Originally spotted in the documentation, it mainly affects code comments but also Atmel SAM3/SAM4/SAMV, NiietCM4 and SiM3x flash driver output. Found via: git grep -i "Cortex " git grep -i "Cortex-" | grep -v "Cortex-" | grep -v ".cpu" git grep -i "CortexM" Change-Id: Ic7b6ca85253e027f6f0f751c628d1a2a391fe914 Signed-off-by: Andreas Färber <afaerber@suse.de> Reviewed-on: http://openocd.zylin.com/3483 Tested-by: jenkins Reviewed-by: Marc Schink <openocd-dev@marcschink.de> Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
54 lines
1.1 KiB
INI
54 lines
1.1 KiB
INI
# MB9BF506
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# Fujitsu Cortex-M3 with 512kB Flash and 64kB RAM
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source [find target/swj-dp.tcl]
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if { [info exists CHIPNAME] } {
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set _CHIPNAME $CHIPNAME
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} else {
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set _CHIPNAME mb9bfxx6
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}
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if { [info exists ENDIAN] } {
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set _ENDIAN $ENDIAN
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} else {
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set _ENDIAN little
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}
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if { [info exists CPUTAPID] } {
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set _CPUTAPID $CPUTAPID
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} else {
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set _CPUTAPID 0x4ba00477
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}
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# delays on reset lines
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adapter_nsrst_delay 100
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if {[using_jtag]} {
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jtag_ntrst_delay 100
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}
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# Fujitsu Cortex-M3 reset configuration
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reset_config trst_only
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swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
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set _TARGETNAME $_CHIPNAME.cpu
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target create $_TARGETNAME cortex_m -endian $_ENDIAN -chain-position $_TARGETNAME
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# MB9BF506 has 64kB of SRAM on its main system bus
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$_TARGETNAME configure -work-area-phys 0x1FFF8000 -work-area-size 0x10000 -work-area-backup 0
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# MB9BF506 has 512kB internal FLASH
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set _FLASHNAME $_CHIPNAME.flash
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flash bank $_FLASHNAME fm3 0 0 0 0 $_TARGETNAME
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# 4MHz / 6 = 666kHz, so use 500
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adapter_khz 500
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if {![using_hla]} {
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# if srst is not fitted use SYSRESETREQ to
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# perform a soft reset
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cortex_m reset_config sysresetreq
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}
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