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As found on the Parallella-I board SKU A101020. Change-Id: Ie7e7a36325926d67fbe555b46a9be8a74fac8dba Signed-off-by: Andreas Färber <afaerber@suse.de> Reviewed-on: http://openocd.zylin.com/2729 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
27 lines
824 B
INI
27 lines
824 B
INI
#
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# Xilinx Zynq-7000 All Programmable SoC
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#
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# http://www.xilinx.com/products/silicon-devices/soc/zynq-7000/index.htm
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#
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set _CHIPNAME zynq
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set _TARGETNAME $_CHIPNAME.cpu
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jtag newtap zynq_pl bs -irlen 6 -ircapture 0x1 -irmask 0x03 \
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-expected-id 0x23727093 \
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-expected-id 0x13722093 \
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-expected-id 0x03727093
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jtag newtap $_CHIPNAME dap -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id 0x4ba00477
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target create ${_TARGETNAME}0 cortex_a -chain-position $_CHIPNAME.dap \
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-coreid 0 -dbgbase 0x80090000
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target create ${_TARGETNAME}1 cortex_a -chain-position $_CHIPNAME.dap \
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-coreid 1 -dbgbase 0x80092000
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target smp ${_TARGETNAME}0 ${_TARGETNAME}1
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adapter_khz 1000
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${_TARGETNAME}0 configure -event reset-assert-post "cortex_a dbginit"
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${_TARGETNAME}1 configure -event reset-assert-post "cortex_a dbginit"
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