Matthias Welwarsky dd60dd84f2 icepick-d: extend access to core control register ... The ICEPick-D jtag router has core control registers that provide the same (or similar) functionality as the tap control register, for individual cores accessible through the same tap (e.g. through a DAP). Core control registers are located at address "0x60 + core-id" of the ROUTER address space (IR=ROUTER). It is sometimes helpful or even necessary to modify the core control register. This patch renames the "icepick_d_coreid" function to the more appropriate "icepick_d_core_control" and adds a "value" argument that allows writing of arbitrary value. "icepick_d_tapenable" is extended by an optional value argument so that core control can be written as the tap is enabled. Change-Id: I0e7f91b596cb5075364c6c233348508f58e0a901 Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com> Reviewed-on: http://openocd.zylin.com/4141 Tested-by: jenkins Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>		2018-02-21 08:19:45 +00:00
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board	ftdi swd: disable SWD output pin during input	2018-01-13 11:37:13 +00:00
chip
cpld	jtagspi: new protocol that includes transfer length	2018-01-13 19:36:42 +00:00
cpu/arm
fpga	tcl/fpga: add config file for Altera 10M50 FPGA (MAX10 family)	2016-08-14 02:05:18 +01:00
interface	tcl: interface: harmonise RPi configs	2018-01-30 07:39:24 +00:00
target	icepick-d: extend access to core control register	2018-02-21 08:19:45 +00:00
test
tools	tcl/board: add Linksys WAG200G config	2016-10-17 09:16:33 +01:00
bitsbytes.tcl
mem_helper.tcl	tcl: add mrb command to mem_helper.tcl	2016-07-17 22:36:47 +01:00
memory.tcl	target: add "phys" argument to mem2array, array2mem	2016-08-09 14:32:12 +01:00
mmr_helpers.tcl