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git://git.code.sf.net/p/openocd/code
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30b0e9af8d
Added support for TMS570LC43xx series parts. This uses the pre-existing ti_tms570.cfg parent config. In ti_tms570.cfg, dbgbase was changed. Note 1: Based on the following TI E2E post, the previous dbgbase was wrong and the new value isn't due to a difference in parts. Link: https://e2e.ti.com/support/microcontrollers/arm-based-microcontrollers-group/arm-based-microcontrollers/f/arm-based-microcontrollers-forum/1106954/tms570ls3137-debugging-with-openocd Note 2: Both the previous dbgbase and the one suggested in the TI E2E post have the 2 LSB set. In the current version of OpenOCD, this will cause cortex_a_read_cpu_memory_fast and cortex_a_write_cpu_memory_fast to fail due to an alignment checks in mem_ap_<read/write>_buf_noincr()->mem_ap_<read/write>(). In all other uses of dbgbase for arm cortex parts, the 2 LSB are masked and ignored. Change-Id: Ic936722e5a4cfc7161b0df1fe3325ee12fd901c6 Signed-off-by: Phil Kirkpatrick <p.kirkpatrick@reflexaerospace.com> Reviewed-on: https://review.openocd.org/c/openocd/+/7682 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
68 lines
1.7 KiB
INI
68 lines
1.7 KiB
INI
# SPDX-License-Identifier: GPL-2.0-or-later
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adapter speed 1500
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if { [info exists CHIPNAME] } {
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set _CHIPNAME $CHIPNAME
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} else {
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set _CHIPNAME tms570
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}
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if { [info exists ENDIAN] } {
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set _ENDIAN $ENDIAN
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} else {
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set _ENDIAN big
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}
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# TMS570 has an ICEpick-C on which we need the router commands.
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source [find target/icepick.cfg]
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# Main DAP
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# DAP_TAPID should be set before source-ing this file
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if { [info exists DAP_TAPID] } {
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set _DAP_TAPID $DAP_TAPID
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}
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jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_DAP_TAPID -disable -ignore-version
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jtag configure $_CHIPNAME.cpu -event tap-enable "icepick_c_tapenable $_CHIPNAME.jrc 0"
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# ICEpick-C (JTAG route controller)
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# JRC_TAPID should be set before source-ing this file
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if { [info exists JRC_TAPID] } {
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set _JRC_TAPID $JRC_TAPID
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}
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set _JRC_TAPID2 0x0B7B302F
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set _JRC_TAPID3 0x0B95502F
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set _JRC_TAPID4 0x0B97102F
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set _JRC_TAPID5 0x0D8A002F
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set _JRC_TAPID6 0x0B8A002F
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jtag newtap $_CHIPNAME jrc -irlen 6 -ircapture 0x1 -irmask 0x3f \
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-expected-id $_JRC_TAPID \
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-expected-id $_JRC_TAPID2 \
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-expected-id $_JRC_TAPID3 \
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-expected-id $_JRC_TAPID4 \
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-expected-id $_JRC_TAPID5 \
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-expected-id $_JRC_TAPID6 \
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-ignore-version
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jtag configure $_CHIPNAME.jrc -event setup "jtag tapenable $_CHIPNAME.cpu"
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jtag configure $_CHIPNAME.jrc -event post-reset "runtest 100"
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dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
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# Cortex-R4 target
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set _TARGETNAME $_CHIPNAME.cpu
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target create $_TARGETNAME cortex_r4 -endian $_ENDIAN \
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-dap $_CHIPNAME.dap -coreid 0 -dbgbase 0x80001000
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# TMS570 uses quirky BE-32 mode
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$_CHIPNAME.dap ti_be_32_quirks 1
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$_TARGETNAME configure -event "reset-assert" {
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global _CHIPNAME
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# assert warm system reset through ICEPick
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icepick_c_wreset $_CHIPNAME.jrc
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}
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