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By default pic32mx starts after any reset with 1 wait state for RAM access/exec. It can be changed to 0 wait states by clearing the BMXWSDRM bit (bit 6) in BMXCON register. With 0 wait states near doubles the execution speed. CRC check sum can be done much faster increasing verify_image speed. Fast data transfer also works with a bit higher scan rate, up to 1500 Khz. This option can be set at any time with mww 0xbf882004 0x40 or cleared with mww 0xbf882008 0x40. Some numbers for FTDI/HS with current devel code and a elf file: Core clock / wait states verify_image speed ------------------------------------|------------------------------ 4 Mhz / 1 21 KiB/s 4 Mhz / 0 36 KiB/s 8 Mhz / 1 37 KiB/s 8 Mhz / 0 57 KiB/s Change-Id: I4092ad0f3753f72f77108718d0ed3a3ab84e3b23 Signed-off-by: Salvador Arroyo <sarroyofdez@yahoo.es> Reviewed-on: http://openocd.zylin.com/1141 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk> Reviewed-by: Xiaofan <xiaofanc@gmail.com> |
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.. | ||
aduc702x.cfg | ||
am335x.cfg | ||
amdm37x.cfg | ||
ar71xx.cfg | ||
at32ap7000.cfg | ||
at91r40008.cfg | ||
at91rm9200.cfg | ||
at91sam3ax_4x.cfg | ||
at91sam3ax_8x.cfg | ||
at91sam3ax_xx.cfg | ||
at91sam3nXX.cfg | ||
at91sam3sXX.cfg | ||
at91sam3u1c.cfg | ||
at91sam3u1e.cfg | ||
at91sam3u2c.cfg | ||
at91sam3u2e.cfg | ||
at91sam3u4c.cfg | ||
at91sam3u4e.cfg | ||
at91sam3uxx.cfg | ||
at91sam3XXX.cfg | ||
at91sam4sXX.cfg | ||
at91sam4XXX.cfg | ||
at91sam7se512.cfg | ||
at91sam7sx.cfg | ||
at91sam7x256.cfg | ||
at91sam7x512.cfg | ||
at91sam9.cfg | ||
at91sam9g10.cfg | ||
at91sam9g20.cfg | ||
at91sam9g45.cfg | ||
at91sam9rl.cfg | ||
at91sam9260_ext_RAM_ext_flash.cfg | ||
at91sam9260.cfg | ||
at91sam9261.cfg | ||
at91sam9263.cfg | ||
atmega128.cfg | ||
avr32.cfg | ||
c100.cfg | ||
c100config.tcl | ||
c100helper.tcl | ||
c100regs.tcl | ||
cs351x.cfg | ||
davinci.cfg | ||
dragonite.cfg | ||
dsp56321.cfg | ||
dsp568013.cfg | ||
dsp568037.cfg | ||
efm32_stlink.cfg | ||
epc9301.cfg | ||
faux.cfg | ||
feroceon.cfg | ||
fm3.cfg | ||
hilscher_netx10.cfg | ||
hilscher_netx50.cfg | ||
hilscher_netx500.cfg | ||
icepick.cfg | ||
imx6.cfg | ||
imx21.cfg | ||
imx25.cfg | ||
imx27.cfg | ||
imx28.cfg | ||
imx31.cfg | ||
imx35.cfg | ||
imx51.cfg | ||
imx53.cfg | ||
imx.cfg | ||
is5114.cfg | ||
ixp42x.cfg | ||
k40.cfg | ||
k60.cfg | ||
lpc2xxx.cfg | ||
lpc17xx.cfg | ||
lpc1751.cfg | ||
lpc1752.cfg | ||
lpc1754.cfg | ||
lpc1756.cfg | ||
lpc1758.cfg | ||
lpc1759.cfg | ||
lpc1763.cfg | ||
lpc1764.cfg | ||
lpc1765.cfg | ||
lpc1766.cfg | ||
lpc1767.cfg | ||
lpc1768.cfg | ||
lpc1769.cfg | ||
lpc1788.cfg | ||
lpc1850.cfg | ||
lpc2103.cfg | ||
lpc2124.cfg | ||
lpc2129.cfg | ||
lpc2148.cfg | ||
lpc2294.cfg | ||
lpc2378.cfg | ||
lpc2460.cfg | ||
lpc2478.cfg | ||
lpc2900.cfg | ||
lpc3131.cfg | ||
lpc3250.cfg | ||
lpc4350.cfg | ||
mc13224v.cfg | ||
nuc910.cfg | ||
omap2420.cfg | ||
omap3530.cfg | ||
omap4430.cfg | ||
omap4460.cfg | ||
omap5912.cfg | ||
omapl138.cfg | ||
pic32mx.cfg | ||
pxa3xx.cfg | ||
pxa255.cfg | ||
pxa270.cfg | ||
readme.txt | ||
samsung_s3c2410.cfg | ||
samsung_s3c2440.cfg | ||
samsung_s3c2450.cfg | ||
samsung_s3c4510.cfg | ||
samsung_s3c6410.cfg | ||
sharp_lh79532.cfg | ||
smp8634.cfg | ||
spear3xx.cfg | ||
stellaris_icdi.cfg | ||
stellaris.cfg | ||
stm32_stlink.cfg | ||
stm32f0x_stlink.cfg | ||
stm32f1x_stlink.cfg | ||
stm32f1x.cfg | ||
stm32f2x_stlink.cfg | ||
stm32f2x.cfg | ||
stm32f3x_stlink.cfg | ||
stm32f3x.cfg | ||
stm32f4x_stlink.cfg | ||
stm32f4x.cfg | ||
stm32l.cfg | ||
stm32lx_dual_bank.cfg | ||
stm32lx_stlink.cfg | ||
stm32xl.cfg | ||
str710.cfg | ||
str730.cfg | ||
str750.cfg | ||
str912.cfg | ||
swj-dp.tcl | ||
test_reset_syntax_error.cfg | ||
test_syntax_error.cfg | ||
ti_calypso.cfg | ||
ti_dm355.cfg | ||
ti_dm365.cfg | ||
ti_dm6446.cfg | ||
ti-ar7.cfg | ||
tmpa900.cfg | ||
tmpa910.cfg | ||
u8500.cfg |
Prerequisites: The users of OpenOCD as well as computer programs interacting with OpenOCD are expecting that certain commands do the same thing across all the targets. Rules to follow when writing scripts: 1. The configuration script should be defined such as , for example, the following sequences are working: reset flash info <bank> and reset flash erase_address <start> <len> and reset init load In most cases this can be accomplished by specifying the default startup mode as reset_init (target command in the configuration file). 2. If the target is correctly configured, flash must be writable without any other helper commands. It is assumed that all write-protect mechanisms should be disabled. 3. The configuration scripts should be defined such as the binary that was written to flash verifies (turn off remapping, checksums, etc...) flash write_image [file] <parameters> verify_image [file] <parameters> 4. adapter_khz sets the maximum speed (or alternatively RCLK). If invoked multiple times only the last setting is used. interface/xxx.cfg files are always executed *before* target/xxx.cfg files, so any adapter_khz in interface/xxx.cfg will be overridden by target/xxx.cfg. adapter_khz in interface/xxx.cfg would then, effectively, set the default JTAG speed. Note that a target/xxx.cfg file can invoke another target/yyy.cfg file, so one can create target subtype configurations where e.g. only amount of DRAM, oscillator speeds differ and having a single config file for the default/common settings.