mirror of
git://git.code.sf.net/p/openocd/code
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also contains target configuration for the Xilinx UltraScale+ platform Change-Id: I6300cbc85c1ed71df71d8aaca59500bbf18f0093 Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com> Reviewed-on: http://openocd.zylin.com/4467 Tested-by: jenkins Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
17 lines
343 B
INI
17 lines
343 B
INI
#
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# AVNET UltraZED EG StarterKit
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# UlraScale-EG plus IO Carrier with on-board digilent smt2
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#
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source [find interface/ftdi/digilent_jtag_smt2_nc.cfg]
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# jtag transport only
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transport select jtag
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# reset lines are not wired
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reset_config none
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# slow default clock
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adapter_khz 1000
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set CHIPNAME uscale
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source [find target/xilinx_ultrascale.cfg]
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