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git://git.code.sf.net/p/openocd/code
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6eb18b307a
Change-Id: I109297aa480b3474f1251571cb8e1a0baa1442fd Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk> Reviewed-on: http://openocd.zylin.com/195 Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
64 lines
2.7 KiB
ArmAsm
64 lines
2.7 KiB
ArmAsm
/***************************************************************************
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* Copyright (C) 2010 by Spencer Oliver *
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* spen@spen-soft.co.uk *
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* *
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* Copyright (C) 2011 Øyvind Harboe *
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* oyvind.harboe@zylin.com *
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* *
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* This program is free software; you can redistribute it and/or modify *
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* it under the terms of the GNU General Public License as published by *
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* the Free Software Foundation; either version 2 of the License, or *
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* (at your option) any later version. *
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* *
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* This program is distributed in the hope that it will be useful, *
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* but WITHOUT ANY WARRANTY; without even the implied warranty of *
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
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* GNU General Public License for more details. *
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* *
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* You should have received a copy of the GNU General Public License *
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* along with this program; if not, write to the *
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* Free Software Foundation, Inc., *
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* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
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***************************************************************************/
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// Build : arm-eabi-gcc -c stm32f2xxx.S
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.text
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.syntax unified
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.cpu cortex-m3
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.thumb
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.thumb_func
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.global write
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/*
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r0 - source address
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r1 - target address
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r2 - count (halfword-16bit)
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r3 - result out
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r4 - flash base
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*/
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#define STM32_FLASH_CR_OFFSET 0x10 /* offset of CR register in FLASH struct */
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#define STM32_FLASH_SR_OFFSET 0x0c /* offset of CR register in FLASH struct */
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write:
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write_half_word:
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ldr r3, STM32_PROG16
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str r3, [r4, #STM32_FLASH_CR_OFFSET]
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ldrh r3, [r0], #0x02 /* read one half-word from src, increment ptr */
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strh r3, [r1], #0x02 /* write one half-word from src, increment ptr */
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busy:
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ldr r3, [r4, #STM32_FLASH_SR_OFFSET]
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tst r3, #0x10000 /* BSY (bit0) == 1 => operation in progress */
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beq busy /* wait more... */
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tst r3, #0xf0 /* PGSERR | PGPERR | PGAERR | WRPERR */
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bne exit /* fail... */
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subs r2, r2, #0x01 /* decrement counter */
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bne write_half_word /* write next half-word if anything left */
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exit:
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bkpt #0x00
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STM32_PROG16: .word 0x101 /* PG | PSIZE_16*/
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