mirror of
git://git.code.sf.net/p/openocd/code
synced 2025-07-20 03:54:05 +10:00
3e6f9e8d1e
The semantics of "-work-area-virt 0" (or phys) changed with the patch to require specifying physical or virtrual work area addresses. Specifying zero was previously a NOP. Now it means that address zero is valid. This patch addresses three related issues: - MMU-less processors should never specify work-area-virt; remove those specifications. Such processors include ARM7TDMI, Cortex-M3, and ARM966. - MMU-equipped processors *can* specify work-area-virt... but zero won't be appropriate, except in mischievous contexts (which hide null pointer exceptions). Remove those specs from those processors too. If any of those mappings is valid, someone will need to submit a patch adding it ... along with a comment saying what OS provides the mapping, and in which context. Example, say "works with Linux 2.6.30+, in kernel mode". (Note that ARM Linux doesn't map kernel memory to zero ...) - Clarify docs on that "-virt" and other work area stuff. Seems to me work-area-virt is quite problematic; not every operating system provides such static mappings; if they do, they're not in every MMU context... Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
99 lines
2.3 KiB
INI
99 lines
2.3 KiB
INI
# A PXA255 test board with SST 39LF400A flash
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#
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# At reset the memory map is as follows. Note that
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# the memory map changes later on as the application
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# starts...
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#
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# RAM at 0x4000000
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# Flash at 0x00000000
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#
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source [find target/pxa255.cfg]
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# Target name is set by above
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$_TARGETNAME configure -work-area-phys 0x4000000 -work-area-size 0x4000 -work-area-backup 0
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# flash bank <driver> <base> <size> <chip_width> <bus_width> <target> [options]
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flash bank cfi 0x00000000 0x80000 2 2 $_TARGETNAME jedec_probe
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proc pxa255_sst_init {} {
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xscale cp15 15 0x00002001 #Enable CP0 and CP13 access
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#
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# setup GPIO
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#
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mww 0x40E00018 0x00008000 #CPSR0
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sleep 20
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mww 0x40E0001C 0x00000002 #GPSR1
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sleep 20
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mww 0x40E00020 0x00000008 #GPSR2
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sleep 20
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mww 0x40E0000C 0x00008000 #GPDR0
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sleep 20
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mww 0x40E00054 0x80000000 #GAFR0_L
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sleep 20
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mww 0x40E00058 0x00188010 #GAFR0_H
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sleep 20
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mww 0x40E0005C 0x60908018 #GAFR1_L
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sleep 20
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mww 0x40E0000C 0x0280E000 #GPDR0
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sleep 20
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mww 0x40E00010 0x821C88B2 #GPDR1
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sleep 20
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mww 0x40E00014 0x000F03DB #GPDR2
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sleep 20
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mww 0x40E00000 0x000F03DB #GPLR0
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sleep 20
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mww 0x40F00004 0x00000020 #PSSR
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sleep 20
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#
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# setup memory controller
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#
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mww 0x48000008 0x01111998 #MSC0
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sleep 20
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mww 0x48000010 0x00047ff0 #MSC2
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sleep 20
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mww 0x48000014 0x00000000 #MECR
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sleep 20
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mww 0x48000028 0x00010504 #MCMEM0
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sleep 20
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mww 0x4800002C 0x00010504 #MCMEM1
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sleep 20
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mww 0x48000030 0x00010504 #MCATT0
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sleep 20
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mww 0x48000034 0x00010504 #MCATT1
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sleep 20
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mww 0x48000038 0x00004715 #MCIO0
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sleep 20
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mww 0x4800003C 0x00004715 #MCIO1
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sleep 20
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#
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mww 0x48000004 0x03CA4018 #MDREF
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sleep 20
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mww 0x48000004 0x004B4018 #MDREF
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sleep 20
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mww 0x48000004 0x000B4018 #MDREF
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sleep 20
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mww 0x48000004 0x000BC018 #MDREF
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sleep 20
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mww 0x48000000 0x00001AC8 #MDCNFG
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sleep 20
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sleep 20
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mww 0x48000000 0x00001AC9 #MDCNFG
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sleep 20
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mww 0x48000040 0x00000000 #MDMRS
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sleep 20
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}
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$_TARGETNAME configure -event reset-init {pxa255_sst_init}
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reset_config trst_and_srst
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jtag_nsrst_delay 200
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jtag_ntrst_delay 200
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#xscale debug_handler 0 0xFFFF0800 # debug handler base address
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