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41c1af7c67
This is clearly noted in the hardware spec (section 5.2.3); it works around a chip erratum: "If the MPU_RESET signal is used, it may cause the EMIFS bus to lock." I seem to have a board with such an initial build. The chip is labeled XOMAP. Presumably, parts without that "X" prefix (eXperimental) resolve this. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
33 lines
1.1 KiB
INI
33 lines
1.1 KiB
INI
# http://omap.spectrumdigital.com/osk5912/
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source [find target/omap5912.cfg]
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# NOTE: this assumes you're using the ARM 20-pin ("Multi-ICE")
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# JTAG connector, and accordingly have J1 connecting pins 1 & 2.
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# The TI-14 pin needs "trst_only", and J1 connecting 2 & 3.
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reset_config trst_and_srst separate
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# NOTE: boards with XOMAP parts wire nSRST to nPWRON_RESET.
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# That resets everything -- including JTAG and EmbeddedICE.
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# So they must use "reset_config srst_pulls_trst".
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# NOTE: an expansion board could add a trace connector ... if
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# it does, change this appropriately. And reset_config too,
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# assuming JTAG_DIS reroutes JTAG to that connector.
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etm config $_TARGETNAME 8 demultiplexed full dummy
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etm_dummy config $_TARGETNAME
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# standard boards populate two 16 MB chips, but manufacturing
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# options or an expansion board could change this config.
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flash bank cfi 0x00000000 0x01000000 2 2 $_TARGETNAME
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flash bank cfi 0x01000000 0x01000000 2 2 $_TARGETNAME
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proc osk5912_init {} {
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omap5912_reset
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# detect flash
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flash probe 0
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flash probe 1
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}
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$_TARGETNAME configure -event reset-init { osk5912_init }
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