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abd78a0ff8
This allows for programming the PL part of the Xilinx Zynq 7000 Change-Id: I89e86c0f381951091f6948c46802d17d7f1f3500 Signed-off-by: Moritz Fischer <moritz.fischer@ettus.com> Reviewed-on: http://openocd.zylin.com/4177 Tested-by: jenkins Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
49 lines
1.3 KiB
INI
49 lines
1.3 KiB
INI
#
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# Xilinx Zynq-7000 All Programmable SoC
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#
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# http://www.xilinx.com/products/silicon-devices/soc/zynq-7000/index.htm
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#
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set _CHIPNAME zynq
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set _TARGETNAME $_CHIPNAME.cpu
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jtag newtap zynq_pl bs -irlen 6 -ircapture 0x1 -irmask 0x03 \
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-expected-id 0x23727093 \
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-expected-id 0x13722093 \
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-expected-id 0x03727093 \
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-expected-id 0x03736093
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jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id 0x4ba00477
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dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
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target create ${_TARGETNAME}0 cortex_a -dap $_CHIPNAME.dap \
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-coreid 0 -dbgbase 0x80090000
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target create ${_TARGETNAME}1 cortex_a -dap $_CHIPNAME.dap \
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-coreid 1 -dbgbase 0x80092000
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target smp ${_TARGETNAME}0 ${_TARGETNAME}1
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adapter_khz 1000
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${_TARGETNAME}0 configure -event reset-assert-post "cortex_a dbginit"
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${_TARGETNAME}1 configure -event reset-assert-post "cortex_a dbginit"
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pld device virtex2 zynq_pl.bs 1
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set XC7_JSHUTDOWN 0x0d
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set XC7_JPROGRAM 0x0b
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set XC7_JSTART 0x0c
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set XC7_BYPASS 0x3f
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proc zynqpl_program {tap} {
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global XC7_JSHUTDOWN XC7_JPROGRAM XC7_JSTART XC7_BYPASS
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irscan $tap $XC7_JSHUTDOWN
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irscan $tap $XC7_JPROGRAM
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runtest 60000
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#JSTART prevents this from working...
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#irscan $tap $XC7_JSTART
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runtest 2000
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irscan $tap $XC7_BYPASS
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runtest 2000
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}
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