mirror of
git://git.code.sf.net/p/openocd/code
synced 2025-07-21 00:42:15 +10:00
ba96fc3e9d
add reset-init script to allow ram execution from reset, this is required for ejtag fastdata access. Signed-off-by: Spencer Oliver <ntfreak@users.sourceforge.net>
59 lines
1.4 KiB
INI
59 lines
1.4 KiB
INI
|
|
if { [info exists CHIPNAME] } {
|
|
set _CHIPNAME $CHIPNAME
|
|
} else {
|
|
set _CHIPNAME pic32mx
|
|
}
|
|
|
|
if { [info exists ENDIAN] } {
|
|
set _ENDIAN $ENDIAN
|
|
} else {
|
|
set _ENDIAN little
|
|
}
|
|
|
|
if { [info exists CPUTAPID ] } {
|
|
set _CPUTAPID $CPUTAPID
|
|
} else {
|
|
# force an error till we get a good number
|
|
set _CPUTAPID 0x30938053
|
|
}
|
|
|
|
jtag_nsrst_delay 100
|
|
jtag_ntrst_delay 100
|
|
|
|
#use combined on interfaces or targets that can't set TRST/SRST separately
|
|
reset_config srst_only
|
|
|
|
#jtag scan chain
|
|
#format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
|
|
jtag newtap $_CHIPNAME cpu -irlen 5 -ircapture 0x1 -irmask 0x1f -expected-id $_CPUTAPID
|
|
|
|
set _TARGETNAME $_CHIPNAME.cpu
|
|
target create $_TARGETNAME mips_m4k -endian $_ENDIAN -chain-position $_TARGETNAME
|
|
|
|
$_TARGETNAME configure -work-area-phys 0xa0000800 -work-area-size 16384 -work-area-backup 0
|
|
|
|
$_TARGETNAME configure -event reset-init {
|
|
#
|
|
# from reset the pic32 cannot execute code in ram - enable ram execution
|
|
# minimum offset from start of ram is 2k
|
|
#
|
|
|
|
# BMXCON
|
|
mww 0xbf882000 0x001f0040
|
|
# BMXDKPBA: 0xa0000800
|
|
mww 0xbf882010 0x00000800
|
|
# BMXDUDBA
|
|
mww 0xbf882020 0x00004000
|
|
# BMXDUPBA
|
|
mww 0xbf882030 0x00004000
|
|
}
|
|
|
|
set _FLASHNAME $_CHIPNAME.flash
|
|
flash bank $_FLASHNAME pic32mx 0xbd000000 0 0 0 $_TARGETNAME
|
|
set _FLASHNAME $_CHIPNAME.flash
|
|
flash bank $_FLASHNAME pic32mx 0xbfc00000 0 0 0 $_TARGETNAME
|
|
|
|
# For more information about the configuration files, take a look at:
|
|
# openocd.texi
|