mirror of
git://git.code.sf.net/p/openocd/code
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bb25049c39
Change-Id: I44fca55c46fc8f960ba46a0604692ce98909face Signed-off-by: Uwe Bonnes <bon@elektron.ikp.physik.tu-darmstadt.de> Reviewed-on: http://openocd.zylin.com/2939 Tested-by: jenkins Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
82 lines
3.1 KiB
ArmAsm
82 lines
3.1 KiB
ArmAsm
/***************************************************************************
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* Copyright (C) 2010 by Spencer Oliver *
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* spen@spen-soft.co.uk *
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* *
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* Copyright (C) 2011 Øyvind Harboe *
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* oyvind.harboe@zylin.com *
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* *
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* This program is free software; you can redistribute it and/or modify *
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* it under the terms of the GNU General Public License as published by *
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* the Free Software Foundation; either version 2 of the License, or *
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* (at your option) any later version. *
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* *
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* This program is distributed in the hope that it will be useful, *
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* but WITHOUT ANY WARRANTY; without even the implied warranty of *
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
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* GNU General Public License for more details. *
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* *
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* You should have received a copy of the GNU General Public License *
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* along with this program; if not, write to the *
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* Free Software Foundation, Inc., *
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
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***************************************************************************/
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.text
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.syntax unified
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.cpu cortex-m3
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.thumb
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.thumb_func
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/*
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* Params :
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* r0 = workarea start, status (out)
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* r1 = workarea end
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* r2 = target address
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* r3 = count (16bit words)
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* r4 = flash base
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*
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* Clobbered:
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* r6 - temp
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* r7 - rp
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* r8 - wp, tmp
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*/
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#define STM32_FLASH_CR_OFFSET 0x10 /* offset of CR register in FLASH struct */
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#define STM32_FLASH_SR_OFFSET 0x0c /* offset of SR register in FLASH struct */
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wait_fifo:
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ldr r8, [r0, #0] /* read wp */
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cmp r8, #0 /* abort if wp == 0 */
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beq exit
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ldr r7, [r0, #4] /* read rp */
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cmp r7, r8 /* wait until rp != wp */
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beq wait_fifo
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ldr r6, STM32_PROG16
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str r6, [r4, #STM32_FLASH_CR_OFFSET]
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ldrh r6, [r7], #0x02 /* read one half-word from src, increment ptr */
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strh r6, [r2], #0x02 /* write one half-word from src, increment ptr */
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dsb
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busy:
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ldr r6, [r4, #STM32_FLASH_SR_OFFSET]
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tst r6, #0x10000 /* BSY (bit16) == 1 => operation in progress */
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bne busy /* wait more... */
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tst r6, #0xf0 /* PGSERR | PGPERR | PGAERR | WRPERR */
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bne error /* fail... */
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cmp r7, r1 /* wrap rp at end of buffer */
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it cs
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addcs r7, r0, #8 /* skip loader args */
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str r7, [r0, #4] /* store rp */
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subs r3, r3, #1 /* decrement halfword count */
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cbz r3, exit /* loop if not done */
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b wait_fifo
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error:
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movs r1, #0
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str r1, [r0, #4] /* set rp = 0 on error */
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exit:
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mov r0, r6 /* return status in r0 */
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bkpt #0x00
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STM32_PROG16: .word 0x101 /* PG | PSIZE_16*/
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