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678fb4f60b
STM32H7x7 and STM32H7x5 devices contains two cores : CM7 + CM4 The second core creation is only done when * DUAL_CORE variable is set to true * non HLA interface is used A second check for the second core existence is done in cpu1 examine-end Once the second core is detected it gets examined. Furthermore, the script provides a configurable CTI usage in order to halt the cores simultaneously. Tested on Rev X and V devices. PS: the indentation was a mix of spaces and tabs, all changed to tabs. Change-Id: Iad9c30826965ddb9be5dee628bc2e63f953bbcb8 Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com> Reviewed-on: http://openocd.zylin.com/5130 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
17 lines
528 B
INI
17 lines
528 B
INI
# This is an ST NUCLEO-H745ZI-Q board with single STM32H745ZITx chip.
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source [find interface/stlink.cfg]
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transport select hla_swd
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# ST-Link HLA interface do not support multi-AP debugging
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# then setting DUAL_CORE and USE_CTI has no effect, because
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# it will fall back to single core configuration
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set DUAL_CORE 1
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set USE_CTI 1
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source [find target/stm32h7x_dual_bank.cfg]
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# when using ST-Link HLA adapter, DBGMCU accesses are done via AP0
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# unfortunately DBGMCU is not accessible when SRST is asserted
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reset_config srst_only
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