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bea4d65903
ARM semihosting + some custom syscalls implemented for Espressif chips (ESP32, ESP32-S2, ESP32-S3) Signed-off-by: Erhan Kurubas <erhan.kurubas@espressif.com> Change-Id: Ic8174cf1cd344fa16d619b7b8405c9650e869443 Reviewed-on: https://review.openocd.org/c/openocd/+/7074 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
81 lines
1.9 KiB
INI
81 lines
1.9 KiB
INI
# SPDX-License-Identifier: GPL-2.0-or-later
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#
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# The ESP32-S2 only supports JTAG.
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transport select jtag
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set CPU_MAX_ADDRESS 0xFFFFFFFF
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source [find bitsbytes.tcl]
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source [find memory.tcl]
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source [find mmr_helpers.tcl]
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# Source the ESP common configuration file
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source [find target/esp_common.cfg]
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if { [info exists CHIPNAME] } {
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set _CHIPNAME $CHIPNAME
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} else {
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set _CHIPNAME esp32s2
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}
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if { [info exists CPUTAPID] } {
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set _CPUTAPID $CPUTAPID
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} else {
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set _CPUTAPID 0x120034e5
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}
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set _TARGETNAME $_CHIPNAME
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set _CPUNAME cpu
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set _TAPNAME $_CHIPNAME.$_CPUNAME
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jtag newtap $_CHIPNAME $_CPUNAME -irlen 5 -expected-id $_CPUTAPID
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proc esp32s2_memprot_is_enabled { } {
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# IRAM0, DPORT_PMS_PRO_IRAM0_0_REG
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if { [get_mmr_bit 0x3f4c1010 0] != 0 } {
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return 1
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}
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# DRAM0, DPORT_PMS_PRO_DRAM0_0_REG
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if { [get_mmr_bit 0x3f4c1028 0] != 0 } {
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return 1
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}
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# PERI1, DPORT_PMS_PRO_DPORT_0_REG
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if { [get_mmr_bit 0x3f4c103c 0] != 0 } {
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return 1
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}
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# PERI2, DPORT_PMS_PRO_AHB_0_REG
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if { [get_mmr_bit 0x3f4c105c 0] != 0 } {
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return 1
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}
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return 0
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}
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target create $_TARGETNAME esp32s2 -endian little -chain-position $_TAPNAME
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$_TARGETNAME configure -event gdb-attach {
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# necessary to auto-probe flash bank when GDB is connected and generate proper memory map
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halt 1000
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if { [esp32s2_memprot_is_enabled] } {
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# 'reset halt' to disable memory protection and allow flasher to work correctly
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echo "Memory protection is enabled. Reset target to disable it..."
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reset halt
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}
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}
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xtensa maskisr on
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$_TARGETNAME configure -event examine-end {
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# Need to enable to set 'semihosting_basedir'
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arm semihosting enable
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arm semihosting_resexit enable
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if { [info exists _SEMIHOST_BASEDIR] } {
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if { $_SEMIHOST_BASEDIR != "" } {
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arm semihosting_basedir $_SEMIHOST_BASEDIR
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}
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}
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}
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$_TARGETNAME configure -event reset-assert-post { soft_reset_halt }
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gdb_breakpoint_override hard
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source [find target/xtensa-core-esp32s2.cfg]
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