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b2821b6074
With this commit we add tcl configure files for ARCv2 HS Development kit(HSDK). HSDK board has Quad-core ARC HS38 CPU with L1 and L2 caches. Change-Id: I372ef45428c7c7ca1421a6da3e5ed08b86f705e0 Signed-off-by: Evgeniy Didin <didin@synopsys.com> Reviewed-on: http://openocd.zylin.com/5784 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
59 lines
1.9 KiB
Tcl
59 lines
1.9 KiB
Tcl
# Copyright (C) 2015, 2020 Synopsys, Inc.
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# Anton Kolesov <anton.kolesov@synopsys.com>
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# Didin Evgeniy <didin@synopsys.com>
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#
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# SPDX-License-Identifier: GPL-2.0-or-later
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source [find cpu/arc/v2.tcl]
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proc arc_hs_examine_target { target } {
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# Will set current target for us.
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arc_v2_examine_target $target
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}
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proc arc_hs_init_regs { } {
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arc_v2_init_regs
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[target current] configure \
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-event examine-end "arc_hs_examine_target [target current]"
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}
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# Scripts in "target" folder should call this function instead of direct
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# invocation of arc_common_reset.
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proc arc_hs_reset { {target ""} } {
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arc_v2_reset $target
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# Invalidate L2 cache if there is one.
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set l2_config [$target arc jtag get-aux-reg 0x901]
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# Will return 0, if cache is not present and register doesn't exist.
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set l2_ctrl [$target arc jtag get-aux-reg 0x903]
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if { ($l2_config != 0) && (($l2_ctrl & 1) == 0) } {
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puts "L2 cache is present and not disabled"
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# Wait until BUSY bit is 0.
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puts "Invalidating L2 cache..."
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$target arc jtag set-aux-reg 0x905 1
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# Dummy read of SLC_AUX_CACHE_CTRL bit, as described in:
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# https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux-stable.git/commit/arch/arc?id=c70c473396cbdec1168a6eff60e13029c0916854
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set l2_ctrl [$target arc jtag get-aux-reg 0x903]
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set l2_ctrl [$target arc jtag get-aux-reg 0x903]
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while { ($l2_ctrl & 0x100) != 0 } {
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set l2_ctrl [$target arc jtag get-aux-reg 0x903]
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}
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# Flush cache if needed. If SLC_AUX_CACHE_CTRL.IM is 1, then invalidate
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# operation already flushed everything.
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if { ($l2_ctrl & 0x40) == 0 } {
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puts "Flushing L2 cache..."
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$target arc jtag set-aux-reg 0x904 1
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set l2_ctrl [$target arc jtag get-aux-reg 0x903]
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set l2_ctrl [$target arc jtag get-aux-reg 0x903]
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while { [expr $l2_ctrl & 0x100] != 0 } {
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set l2_ctrl [$target arc jtag get-aux-reg 0x903]
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}
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}
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puts "L2 cache has been flushed and invalidated."
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}
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}
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