mirror of
git://git.code.sf.net/p/openocd/code
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f2b4897773
The device has compatible flash macro with STM32F1 family, reuse stm32f1x driver code. Detect non-ARM target - for simplicy test target type name 'riscv' and the address has 32 bits. In case of RISC-V CPU use simple chunked write algo - async algo cannot be used as the core implemented in this device doesn't allow memory access while running. Change-Id: Ie3886fbd8573652691f91a02335812a7300689f7 Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-on: https://review.openocd.org/c/openocd/+/6704 Tested-by: jenkins Reviewed-by: Tim Newsome <tim@sifive.com> |
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| .. | ||
| at91sam7x | ||
| bluenrg-x | ||
| cc26xx | ||
| cc3220sf | ||
| fespi | ||
| fm4 | ||
| fpga | ||
| gd32vf103 | ||
| kinetis | ||
| kinetis_ke | ||
| max32xxx | ||
| msp432 | ||
| npcx | ||
| nrf5 | ||
| sh_qspi | ||
| stm32 | ||
| stmqspi | ||
| xmc1xxx | ||
| armv4_5_cfi_intel_8.s | ||
| armv4_5_cfi_intel_16.s | ||
| armv4_5_cfi_intel_32.s | ||
| armv4_5_cfi_span_8.s | ||
| armv4_5_cfi_span_16_dq7.s | ||
| armv4_5_cfi_span_16.s | ||
| armv4_5_cfi_span_32.s | ||
| armv7m_cfi_span_16_dq7.s | ||
| armv7m_cfi_span_16.s | ||
| armv7m_io.s | ||
| cortex-m0.S | ||
| efm32.S | ||
| k1921vk01t.S | ||
| lpcspifi_erase.S | ||
| lpcspifi_init.S | ||
| lpcspifi_write.S | ||
| mdr32fx.S | ||
| mrvlqspi_write.S | ||
| pic32mx.s | ||
| sim3x.s | ||
| stellaris.s | ||
| str7x.s | ||
| str9x.s | ||