mirror of
git://git.code.sf.net/p/openocd/code
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f5657aa76e
Jimtcl commit 1843b79a03dd ("expr: TIP 526, only support a single
arg") drops the support for multi-argument syntax for the TCL
command 'expr'.
In the TCL scripts distributed with OpenOCD there are 1700+ lines
that should be modified before switching to jimtcl 0.81.
Apply the script below on every script in tcl folder. It fixes
more than 92% of the lines
%<---%<---%<---%<---%<---%<---%<---%<---%<---%<---%<---%<---%<---
#!/usr/bin/perl -Wpi
my $re_sym = qr{[a-z_][a-z0-9_]*}i;
my $re_var = qr{(?:\$|\$::)$re_sym};
my $re_const = qr{0x[0-9a-f]+|[0-9]+|[0-9]*\.[0-9]*}i;
my $re_item = qr{(?:~\s*)?(?:$re_var|$re_const)};
my $re_op = qr{<<|>>|[+\-*/&|]};
my $re_expr = qr{(
(?:\(\s*(?:$re_item|(?-1))\s*\)|$re_item)
\s*$re_op\s*
(?:$re_item|(?-1)|\(\s*(?:$re_item|(?-1))\s*\))
)}x;
# [expr [dict get $regsC100 SYM] + HEXNUM]
s/\[expr (\[dict get $re_var $re_sym\s*\] \+ *$re_const)\]/\[expr \{$1\}\]/;
# [ expr (EXPR) ]
# [ expr EXPR ]
# note: $re_expr captures '$3'
s/\[(\s*expr\s*)\((\s*$re_expr\s*)\)(\s*)\]/\[$1\{$2\}$4\]/;
s/\[(\s*expr\s*)($re_expr)(\s*)\]/\[$1\{$2\}$4\]/;
%<---%<---%<---%<---%<---%<---%<---%<---%<---%<---%<---%<---%<---
Change-Id: I0d6bddc6abf6dd29062f2b4e72b5a2b5080293b9
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/6159
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
96 lines
4.0 KiB
INI
96 lines
4.0 KiB
INI
uplevel #0 [list source [find chip/atmel/at91/at91sam9_sdramc.cfg]]
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uplevel #0 [list source [find chip/atmel/at91/at91_pmc.cfg]]
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uplevel #0 [list source [find chip/atmel/at91/at91_pio.cfg]]
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uplevel #0 [list source [find chip/atmel/at91/at91_rstc.cfg]]
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uplevel #0 [list source [find chip/atmel/at91/at91_wdt.cfg]]
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proc at91sam9_reset_start { } {
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arm7_9 fast_memory_access disable
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jtag_rclk 8
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halt
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wait_halt 10000
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set rstc_mr_val [expr $::AT91_RSTC_KEY]
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set rstc_mr_val [expr {$rstc_mr_val | (5 << 8)}]
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set rstc_mr_val [expr {$rstc_mr_val | $::AT91_RSTC_URSTEN}]
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mww $::AT91_RSTC_MR $rstc_mr_val ;# RSTC_MR : enable user reset.
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}
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proc at91sam9_reset_init { config } {
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mww $::AT91_WDT_MR $config(wdt_mr_val) ;# disable watchdog
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set ckgr_mor [expr {$::AT91_PMC_MOSCEN | (255 << 8)}]
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mww $::AT91_CKGR_MOR $ckgr_mor ;# CKGR_MOR - enable main osc.
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while { [expr [mrw $::AT91_PMC_SR] & $::AT91_PMC_MOSCS] != $::AT91_PMC_MOSCS } { sleep 1 }
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set pllar_val [expr $::AT91_PMC_PLLA_WR_ERRATA] ;# Bit 29 must be 1 when prog
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set pllar_val [expr {$pllar_val | $::AT91_PMC_OUT}]
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set pllar_val [expr {$pllar_val | $::AT91_PMC_PLLCOUNT}]
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set pllar_val [expr ($pllar_val | ($config(master_pll_mul) - 1) << 16)]
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set pllar_val [expr ($pllar_val | $config(master_pll_div))]
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mww $::AT91_CKGR_PLLAR $pllar_val ;# CKGR_PLLA - (18.432MHz/13)*141 = 199.9 MHz
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while { [expr [mrw $::AT91_PMC_SR] & $::AT91_PMC_LOCKA] != $::AT91_PMC_LOCKA } { sleep 1 }
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;# PCK/2 = MCK Master Clock from PLLA
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set mckr_val [expr $::AT91_PMC_CSS_PLLA]
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set mckr_val [expr {$mckr_val | $::AT91_PMC_PRES_1}]
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set mckr_val [expr {$mckr_val | $::AT91SAM9_PMC_MDIV_2}]
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set mckr_val [expr {$mckr_val | $::AT91_PMC_PDIV_1}]
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mww $::AT91_PMC_MCKR $mckr_val ;# PMC_MCKR (MCLK: 0x102 - (CLK/2)MHZ, 0x202 - (CLK/3)MHz)
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while { [expr [mrw $::AT91_PMC_SR] & $::AT91_PMC_MCKRDY] != $::AT91_PMC_MCKRDY } { sleep 1 }
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## switch JTAG clock to highspeed clock
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jtag_rclk 0
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arm7_9 dcc_downloads enable ;# Enable faster DCC downloads
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arm7_9 fast_memory_access enable
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set rstc_mr_val [expr ($::AT91_RSTC_KEY)]
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set rstc_mr_val [expr {$rstc_mr_val | $::AT91_RSTC_URSTEN}]
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mww $::AT91_RSTC_MR $rstc_mr_val ;# user reset enable
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if { [info exists config(sdram_piod)] } {
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set pdr_addr [expr {$::AT91_PIOD + $::PIO_PDR}]
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set pudr_addr [expr {$::AT91_PIOD + $::PIO_PUDR}]
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set asr_addr [expr {$::AT91_PIOD + $::PIO_ASR}]
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mww $pdr_addr 0xffff0000 ;# define PDC[31:16] as DATA[31:16]
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mww $pudr_addr 0xffff0000 ;# no pull-up for D[31:16]
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mww $asr_addr 0xffff0000
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} else {
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set pdr_addr [expr {$::AT91_PIOC + $::PIO_PDR}]
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set pudr_addr [expr {$::AT91_PIOC + $::PIO_PUDR}]
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mww $pdr_addr 0xffff0000 ;# define PDC[31:16] as DATA[31:16]
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mww $pudr_addr 0xffff0000 ;# no pull-up for D[31:16]
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}
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mww $config(matrix_ebicsa_addr) $config(matrix_ebicsa_val)
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mww $::AT91_SDRAMC_MR $::AT91_SDRAMC_MODE_NORMAL ;# SDRAMC_MR Mode register
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mww $::AT91_SDRAMC_TR $config(sdram_tr_val) ;# SDRAMC_TR - Refresh Timer register
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mww $::AT91_SDRAMC_CR $config(sdram_cr_val) ;# SDRAMC_CR - Configuration register
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mww $::AT91_SDRAMC_MDR $::AT91_SDRAMC_MD_SDRAM ;# Memory Device Register -> SDRAM
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mww $::AT91_SDRAMC_MR $::AT91_SDRAMC_MODE_PRECHARGE ;# SDRAMC_MR
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mww $config(sdram_base) 0 ;# SDRAM_BASE
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mww $::AT91_SDRAMC_MR $::AT91_SDRAMC_MODE_REFRESH ;# SDRC_MR
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mww $config(sdram_base) 0 ;# SDRAM_BASE
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mww $config(sdram_base) 0 ;# SDRAM_BASE
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mww $config(sdram_base) 0 ;# SDRAM_BASE
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mww $config(sdram_base) 0 ;# SDRAM_BASE
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mww $config(sdram_base) 0 ;# SDRAM_BASE
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mww $config(sdram_base) 0 ;# SDRAM_BASE
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mww $config(sdram_base) 0 ;# SDRAM_BASE
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mww $config(sdram_base) 0 ;# SDRAM_BASE
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mww $::AT91_SDRAMC_MR $::AT91_SDRAMC_MODE_LMR ;# SDRC_MR
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mww $config(sdram_base) 0 ;# SDRAM_BASE
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mww $::AT91_SDRAMC_MR $::AT91_SDRAMC_MODE_NORMAL ;# SDRC_MR
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mww $config(sdram_base) 0 ;# SDRAM_BASE
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mww $::AT91_SDRAMC_TR 1200 ;# SDRAM_TR
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mww $config(sdram_base) 0 ;# SDRAM_BASE
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mww $::AT91_MATRIX 0xf ;# MATRIX_MCFG - REMAP all masters
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}
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