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git://git.code.sf.net/p/openocd/code
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0c8ec7c826
It's Cortex-Xn, not Cortex Xn or cortex xn or cortex-xn or CORTEX-Xn or CortexXn. Further it's Cortex-M0+, not M0plus. Cf. http://www.arm.com/products/processors/index.php Consistently write it the official way, so that it stops propagating. Originally spotted in the documentation, it mainly affects code comments but also Atmel SAM3/SAM4/SAMV, NiietCM4 and SiM3x flash driver output. Found via: git grep -i "Cortex " git grep -i "Cortex-" | grep -v "Cortex-" | grep -v ".cpu" git grep -i "CortexM" Change-Id: Ic7b6ca85253e027f6f0f751c628d1a2a391fe914 Signed-off-by: Andreas Färber <afaerber@suse.de> Reviewed-on: http://openocd.zylin.com/3483 Tested-by: jenkins Reviewed-by: Marc Schink <openocd-dev@marcschink.de> Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
79 lines
2.0 KiB
INI
79 lines
2.0 KiB
INI
source [find target/icepick.cfg]
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if { [info exists CHIPNAME] } {
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set _CHIPNAME $CHIPNAME
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} else {
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set _CHIPNAME am335x
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}
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# set the taps to be enabled by default. this can be overridden
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# by setting DEFAULT_TAPS in a separate configuration file
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# or directly on the command line.
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if { [info exists DEFAULT_TAPS] } {
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set _DEFAULT_TAPS "$DEFAULT_TAPS"
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} else {
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set _DEFAULT_TAPS "$_CHIPNAME.dap"
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}
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#
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# Main DAP
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#
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if { [info exists DAP_TAPID] } {
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set _DAP_TAPID $DAP_TAPID
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} else {
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set _DAP_TAPID 0x4b6b902f
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}
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jtag newtap $_CHIPNAME dap -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_DAP_TAPID -disable
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jtag configure $_CHIPNAME.dap -event tap-enable "icepick_d_tapenable $_CHIPNAME.jrc 12 0"
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#
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# M3 DAP
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#
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if { [info exists M3_DAP_TAPID] } {
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set _M3_DAP_TAPID $M3_DAP_TAPID
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} else {
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set _M3_DAP_TAPID 0x4b6b902f
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}
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jtag newtap $_CHIPNAME m3_dap -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_M3_DAP_TAPID -disable
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jtag configure $_CHIPNAME.m3_dap -event tap-enable "icepick_d_tapenable $_CHIPNAME.jrc 11 0"
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#
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# ICEpick-D (JTAG route controller)
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#
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if { [info exists JRC_TAPID] } {
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set _JRC_TAPID $JRC_TAPID
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} else {
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set _JRC_TAPID 0x0b94402f
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}
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jtag newtap $_CHIPNAME jrc -irlen 6 -ircapture 0x1 -irmask 0x3f -expected-id $_JRC_TAPID -ignore-version
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jtag configure $_CHIPNAME.jrc -event setup {
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global _DEFAULT_TAPS
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enable_default_taps $_DEFAULT_TAPS
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}
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# some TCK tycles are required to activate the DEBUG power domain
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jtag configure $_CHIPNAME.jrc -event post-reset "runtest 100"
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#
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# helper function that enables all taps passed as argument
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#
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proc enable_default_taps { taps } {
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foreach tap $taps {
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jtag tapenable $tap
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}
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}
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#
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# Cortex-M3 target
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#
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set _TARGETNAME_2 $_CHIPNAME.m3
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target create $_TARGETNAME_2 cortex_m -chain-position $_CHIPNAME.m3_dap
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#
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# Cortex-A8 target
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#
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set _TARGETNAME $_CHIPNAME.cpu
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target create $_TARGETNAME cortex_a -chain-position $_CHIPNAME.dap -dbgbase 0x80001000
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# SRAM: 64K at 0x4030.0000; use the first 16K
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$_TARGETNAME configure -work-area-phys 0x40300000 -work-area-size 0x4000
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