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git://git.code.sf.net/p/openocd/code
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382148e4dd
With the old checkpatch we cannot use the correct format for the SPDX tags in the file .c, in fact the C99 comments are not allowed and we had to use the block comment. With the new checkpatch, let's switch to the correct SPDX format. Change created automatically through the command: sed -i \ 's,^/\* *\(SPDX-License-Identifier: .*[^ ]\) *\*/$,// \1,' \ $(find src/ contrib/ -name \*.c) Change-Id: I6da16506baa7af718947562505dd49606d124171 Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: https://review.openocd.org/c/openocd/+/7153 Tested-by: jenkins
159 lines
4.7 KiB
C
159 lines
4.7 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
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/***************************************************************************
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* Copyright (C) 2005 by Dominic Rath *
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* Dominic.Rath@gmx.de *
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***************************************************************************/
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#ifdef HAVE_CONFIG_H
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#include "config.h"
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#endif
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#include <helper/log.h>
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#include "target.h"
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#include "armv4_5_mmu.h"
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int armv4_5_mmu_translate_va(struct target *target,
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struct armv4_5_mmu_common *armv4_5_mmu, uint32_t va, uint32_t *cb, uint32_t *val)
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{
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uint32_t first_lvl_descriptor = 0x0;
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uint32_t second_lvl_descriptor = 0x0;
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uint32_t ttb;
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int retval;
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retval = armv4_5_mmu->get_ttb(target, &ttb);
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if (retval != ERROR_OK)
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return retval;
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retval = armv4_5_mmu_read_physical(target, armv4_5_mmu,
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(ttb & 0xffffc000) | ((va & 0xfff00000) >> 18),
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4, 1, (uint8_t *)&first_lvl_descriptor);
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if (retval != ERROR_OK)
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return retval;
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first_lvl_descriptor = target_buffer_get_u32(target, (uint8_t *)&first_lvl_descriptor);
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LOG_DEBUG("1st lvl desc: %8.8" PRIx32 "", first_lvl_descriptor);
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if ((first_lvl_descriptor & 0x3) == 0) {
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LOG_ERROR("Address translation failure");
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return ERROR_TARGET_TRANSLATION_FAULT;
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}
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if (!armv4_5_mmu->has_tiny_pages && ((first_lvl_descriptor & 0x3) == 3)) {
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LOG_ERROR("Address translation failure");
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return ERROR_TARGET_TRANSLATION_FAULT;
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}
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if ((first_lvl_descriptor & 0x3) == 2) {
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/* section descriptor */
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*cb = (first_lvl_descriptor & 0xc) >> 2;
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*val = (first_lvl_descriptor & 0xfff00000) | (va & 0x000fffff);
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return ERROR_OK;
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}
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if ((first_lvl_descriptor & 0x3) == 1) {
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/* coarse page table */
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retval = armv4_5_mmu_read_physical(target, armv4_5_mmu,
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(first_lvl_descriptor & 0xfffffc00) | ((va & 0x000ff000) >> 10),
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4, 1, (uint8_t *)&second_lvl_descriptor);
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if (retval != ERROR_OK)
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return retval;
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} else if ((first_lvl_descriptor & 0x3) == 3) {
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/* fine page table */
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retval = armv4_5_mmu_read_physical(target, armv4_5_mmu,
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(first_lvl_descriptor & 0xfffff000) | ((va & 0x000ffc00) >> 8),
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4, 1, (uint8_t *)&second_lvl_descriptor);
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if (retval != ERROR_OK)
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return retval;
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}
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second_lvl_descriptor = target_buffer_get_u32(target, (uint8_t *)&second_lvl_descriptor);
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LOG_DEBUG("2nd lvl desc: %8.8" PRIx32 "", second_lvl_descriptor);
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if ((second_lvl_descriptor & 0x3) == 0) {
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LOG_ERROR("Address translation failure");
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return ERROR_TARGET_TRANSLATION_FAULT;
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}
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/* cacheable/bufferable is always specified in bits 3-2 */
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*cb = (second_lvl_descriptor & 0xc) >> 2;
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if ((second_lvl_descriptor & 0x3) == 1) {
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/* large page descriptor */
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*val = (second_lvl_descriptor & 0xffff0000) | (va & 0x0000ffff);
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return ERROR_OK;
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}
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if ((second_lvl_descriptor & 0x3) == 2) {
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/* small page descriptor */
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*val = (second_lvl_descriptor & 0xfffff000) | (va & 0x00000fff);
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return ERROR_OK;
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}
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if ((second_lvl_descriptor & 0x3) == 3) {
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/* tiny page descriptor */
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*val = (second_lvl_descriptor & 0xfffffc00) | (va & 0x000003ff);
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return ERROR_OK;
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}
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/* should not happen */
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LOG_ERROR("Address translation failure");
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return ERROR_TARGET_TRANSLATION_FAULT;
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}
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int armv4_5_mmu_read_physical(struct target *target,
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struct armv4_5_mmu_common *armv4_5_mmu, uint32_t address,
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uint32_t size, uint32_t count, uint8_t *buffer)
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{
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int retval;
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if (target->state != TARGET_HALTED)
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return ERROR_TARGET_NOT_HALTED;
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/* disable MMU and data (or unified) cache */
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retval = armv4_5_mmu->disable_mmu_caches(target, 1, 1, 0);
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if (retval != ERROR_OK)
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return retval;
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retval = armv4_5_mmu->read_memory(target, address, size, count, buffer);
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if (retval != ERROR_OK)
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return retval;
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/* reenable MMU / cache */
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retval = armv4_5_mmu->enable_mmu_caches(target, armv4_5_mmu->mmu_enabled,
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armv4_5_mmu->armv4_5_cache.d_u_cache_enabled,
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armv4_5_mmu->armv4_5_cache.i_cache_enabled);
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if (retval != ERROR_OK)
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return retval;
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return retval;
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}
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int armv4_5_mmu_write_physical(struct target *target,
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struct armv4_5_mmu_common *armv4_5_mmu, uint32_t address,
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uint32_t size, uint32_t count, const uint8_t *buffer)
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{
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int retval;
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if (target->state != TARGET_HALTED)
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return ERROR_TARGET_NOT_HALTED;
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/* disable MMU and data (or unified) cache */
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retval = armv4_5_mmu->disable_mmu_caches(target, 1, 1, 0);
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if (retval != ERROR_OK)
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return retval;
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retval = armv4_5_mmu->write_memory(target, address, size, count, buffer);
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if (retval != ERROR_OK)
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return retval;
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/* reenable MMU / cache */
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retval = armv4_5_mmu->enable_mmu_caches(target, armv4_5_mmu->mmu_enabled,
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armv4_5_mmu->armv4_5_cache.d_u_cache_enabled,
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armv4_5_mmu->armv4_5_cache.i_cache_enabled);
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if (retval != ERROR_OK)
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return retval;
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return retval;
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}
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