From 3f7c6353c1bc346bcd52aa40cbc0a382999ebf02 Mon Sep 17 00:00:00 2001
From: Stuart Longland <me@vk4msl.id.au>
Date: Sun, 9 Apr 2017 09:17:04 +1000
Subject: [PATCH] ports/attiny85: Remove debugging #if blocks

---
 ports/attiny85/main.c | 70 ++++---------------------------------------
 1 file changed, 5 insertions(+), 65 deletions(-)

diff --git a/ports/attiny85/main.c b/ports/attiny85/main.c
index a197745..1c1d95d 100644
--- a/ports/attiny85/main.c
+++ b/ports/attiny85/main.c
@@ -28,32 +28,16 @@
 #define SAMPLE_LEN	128
 static volatile uint8_t sample_buffer[SAMPLE_LEN];
 static struct fifo_t sample_fifo;
-volatile uint8_t underflow = 0;
 
 struct voice_ch_t poly_voice[16];
 struct poly_synth_t synth;
 
 int main(void) {
-#if 0
-	/* Turn clock speed right up */
-	CLKPR = (1 << CLKPCE);
-
-	/* Turn on all except ADC */
-	PRR = (1 << PRADC);
-
-	/* Start up PLL */
-	PLLCSR = (1 << PLLE);
-	while (!(PLLCSR & (1<<PLOCK)));
-	PLLCSR |= (1<<PCKE);
-#endif
-
-#if 1
 	fifo_init(&sample_fifo, sample_buffer, SAMPLE_LEN);
 	memset(poly_voice, 0, sizeof(poly_voice));
 	synth.voice = poly_voice;
 	synth.enable = 0;
 	synth.mute = 0;
-#endif
 
 	/* Enable output on PB4 (PWM out) */
 	DDRB |= (1 << 4) | (1 << 3);
@@ -73,68 +57,24 @@ int main(void) {
 	OCR0A = (uint8_t)((uint32_t)F_CPU / (8*(uint32_t)SYNTH_FREQ));
 	TIMSK |= (1 << OCIE0A);		/* Enable interrupts */
 
-#if 1
 	/* Configure the synthesizer */
 	synth.enable = 1;
 	voice_wf_set_square(&poly_voice[0].wf, 1000, 127);
 	poly_voice[0].adsr.time_scale = 32;
 	poly_voice[0].adsr.sustain_time = 120;
 	poly_voice[0].adsr.sustain_amp = 255;
-#endif
 
-#if 1
 	sei();
 	while(1) {
-#if 1
-		while (sample_fifo.stored_sz < SAMPLE_LEN) {
-			int16_t s = poly_synth_next(&synth);
-			fifo_write_one(&sample_fifo,
-					128 + (s >> 9));
-#if 1
-			PORTB ^= (1 << 3);
-#endif
-			if (poly_voice[0].adsr.state ==
-					ADSR_STATE_DONE)
-				adsr_reset(&poly_voice[0].adsr);
-			while(underflow);
-		}
-
-#if 0
-		poly_evt.flags = POLY_EVT_TYPE_IFREQ;
-		poly_evt.value += 100;
-		if (poly_evt.value > 2000)
-			poly_evt.value = 100;
-		poly_load(&poly_evt);
-#endif
-#endif
+		if (poly_voice[0].adsr.state ==
+				ADSR_STATE_DONE)
+			adsr_reset(&poly_voice[0].adsr);
 	}
-#else
-	while (1) {
-		int i;
-		for (i = 0; i < 255; i++) {
-			OCR1B = i;
-			_delay_us(100);
-		}
-		for (i = 255; i > 0; i--) {
-			OCR1B = i;
-			_delay_us(100);
-		}
-		PORTB ^= (1 << 3);
-	}
-#endif
 	return 0;
 }
 
 ISR(TIM0_COMPA_vect) {
-#if 1
-	uint8_t sample = fifo_read_one(&sample_fifo);
-	if (sample >= 0) {
-		OCR1B = sample;
-	} else {
-		OCR1B = 128;
-		underflow = 1;
-	}
-#else
+	int8_t s = poly_synth_next(&synth);
+	OCR1B = s + 128;
 	PORTB ^= (1 << 3);
-#endif
 }