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ARM: SoC fixes for 6.7, part 3

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A couple of platforms have some last-minute fixes for 6.7, in particular
 
  - riscv gets some fixes for noncoherent DMA on the renesas and thead
    platforms and dts fix for SPI on the visionfive 2 board
 
  - Qualcomm Snapdragon gets three dts fixes to address board specific
    regressions on the pmic and gpio nodes
 
  - Rockchip platforms get multiple dts fixes to address issues on
    the recent rk3399 platform as well as the older rk3128 platform
    that apparently regressed a while ago.
 
  - TI OMAP gets some trivial code and dts fixes and a regression fix
    for the omap1 ams-delta modem
 
  - NXP i.MX firmware has one fix for a use-after-free but in its
    error handling.
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Merge tag 'soc-fixes-6.7-3' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc

Pull ARM SoC fixes from Arnd Bergmann:
 "A couple of platforms have some last-minute fixes, in particular:

   - riscv gets some fixes for noncoherent DMA on the renesas and thead
     platforms and dts fix for SPI on the visionfive 2 board

   - Qualcomm Snapdragon gets three dts fixes to address board specific
     regressions on the pmic and gpio nodes

   - Rockchip platforms get multiple dts fixes to address issues on the
     recent rk3399 platform as well as the older rk3128 platform that
     apparently regressed a while ago.

   - TI OMAP gets some trivial code and dts fixes and a regression fix
     for the omap1 ams-delta modem

   - NXP i.MX firmware has one fix for a use-after-free but in its error
     handling"

* tag 'soc-fixes-6.7-3' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (25 commits)
  soc: renesas: ARCH_R9A07G043 depends on !RISCV_ISA_ZICBOM
  riscv: only select DMA_DIRECT_REMAP from RISCV_ISA_ZICBOM and ERRATA_THEAD_PBMT
  riscv: RISCV_NONSTANDARD_CACHE_OPS shouldn't depend on RISCV_DMA_NONCOHERENT
  riscv: dts: thead: set dma-noncoherent to soc bus
  arm64: dts: rockchip: Fix i2s0 pin conflict on ROCK Pi 4 boards
  arm64: dts: rockchip: Add i2s0-2ch-bus-bclk-off pins to RK3399
  clk: ti: Fix missing omap5 mcbsp functional clock and aliases
  clk: ti: Fix missing omap4 mcbsp functional clock and aliases
  ARM: OMAP1: ams-delta: Fix MODEM initialization failure
  soc: renesas: Make ARCH_R9A07G043 depend on required options
  riscv: dts: starfive: visionfive 2: correct spi's ss pin
  firmware/imx-dsp: Fix use_after_free in imx_dsp_setup_channels()
  ARM: OMAP: timer32K: fix all kernel-doc warnings
  ARM: omap2: fix a debug printk
  ARM: dts: rockchip: Fix timer clocks for RK3128
  ARM: dts: rockchip: Add missing quirk for RK3128's dma engine
  ARM: dts: rockchip: Add missing arm timer interrupt for RK3128
  ARM: dts: rockchip: Fix i2c0 register address for RK3128
  arm64: dts: rockchip: set codec system-clock-fixed on px30-ringneck-haikou
  arm64: dts: rockchip: use codec as clock master on px30-ringneck-haikou
  ...
This commit is contained in:
Linus Torvalds 2023-10-26 08:17:26 -10:00
commit 3a568e3a96
24 changed files with 127 additions and 119 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
MAINTAINERS
View File

@ -13846,9 +13846,10 @@ F: Documentation/devicetree/bindings/media/amlogic,gx-vdec.yaml
F: drivers/staging/media/meson/vdec/ F: drivers/staging/media/meson/vdec/
METHODE UDPU SUPPORT METHODE UDPU SUPPORT
M: Vladimir Vid <vladimir.vid@sartura.hr> M: Robert Marko <robert.marko@sartura.hr>
S: Maintained S: Maintained
F: arch/arm64/boot/dts/marvell/armada-3720-uDPU.dts F: arch/arm64/boot/dts/marvell/armada-3720-eDPU.dts
F: arch/arm64/boot/dts/marvell/armada-3720-uDPU.*
MHI BUS MHI BUS
M: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> M: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>

18
arch/arm/boot/dts/rockchip/rk3128.dtsi
View File

@ -64,7 +64,8 @@
compatible = "arm,armv7-timer"; compatible = "arm,armv7-timer";
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
arm,cpu-registers-not-fw-configured; arm,cpu-registers-not-fw-configured;
clock-frequency = <24000000>; clock-frequency = <24000000>;
}; };
@ -233,7 +234,7 @@
compatible = "rockchip,rk3128-timer", "rockchip,rk3288-timer"; compatible = "rockchip,rk3128-timer", "rockchip,rk3288-timer";
reg = <0x20044000 0x20>; reg = <0x20044000 0x20>;
interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru PCLK_TIMER>, <&xin24m>; clocks = <&cru PCLK_TIMER>, <&cru SCLK_TIMER0>;
clock-names = "pclk", "timer"; clock-names = "pclk", "timer";
}; };
@ -241,7 +242,7 @@
compatible = "rockchip,rk3128-timer", "rockchip,rk3288-timer"; compatible = "rockchip,rk3128-timer", "rockchip,rk3288-timer";
reg = <0x20044020 0x20>; reg = <0x20044020 0x20>;
interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru PCLK_TIMER>, <&xin24m>; clocks = <&cru PCLK_TIMER>, <&cru SCLK_TIMER1>;
clock-names = "pclk", "timer"; clock-names = "pclk", "timer";
}; };
@ -249,7 +250,7 @@
compatible = "rockchip,rk3128-timer", "rockchip,rk3288-timer"; compatible = "rockchip,rk3128-timer", "rockchip,rk3288-timer";
reg = <0x20044040 0x20>; reg = <0x20044040 0x20>;
interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru PCLK_TIMER>, <&xin24m>; clocks = <&cru PCLK_TIMER>, <&cru SCLK_TIMER2>;
clock-names = "pclk", "timer"; clock-names = "pclk", "timer";
}; };
@ -257,7 +258,7 @@
compatible = "rockchip,rk3128-timer", "rockchip,rk3288-timer"; compatible = "rockchip,rk3128-timer", "rockchip,rk3288-timer";
reg = <0x20044060 0x20>; reg = <0x20044060 0x20>;
interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru PCLK_TIMER>, <&xin24m>; clocks = <&cru PCLK_TIMER>, <&cru SCLK_TIMER3>;
clock-names = "pclk", "timer"; clock-names = "pclk", "timer";
}; };
@ -265,7 +266,7 @@
compatible = "rockchip,rk3128-timer", "rockchip,rk3288-timer"; compatible = "rockchip,rk3128-timer", "rockchip,rk3288-timer";
reg = <0x20044080 0x20>; reg = <0x20044080 0x20>;
interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru PCLK_TIMER>, <&xin24m>; clocks = <&cru PCLK_TIMER>, <&cru SCLK_TIMER4>;
clock-names = "pclk", "timer"; clock-names = "pclk", "timer";
}; };
@ -273,7 +274,7 @@
compatible = "rockchip,rk3128-timer", "rockchip,rk3288-timer"; compatible = "rockchip,rk3128-timer", "rockchip,rk3288-timer";
reg = <0x200440a0 0x20>; reg = <0x200440a0 0x20>;
interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru PCLK_TIMER>, <&xin24m>; clocks = <&cru PCLK_TIMER>, <&cru SCLK_TIMER5>;
clock-names = "pclk", "timer"; clock-names = "pclk", "timer";
}; };
@ -426,7 +427,7 @@
i2c0: i2c@20072000 { i2c0: i2c@20072000 {
compatible = "rockchip,rk3128-i2c", "rockchip,rk3288-i2c"; compatible = "rockchip,rk3128-i2c", "rockchip,rk3288-i2c";
reg = <20072000 0x1000>; reg = <0x20072000 0x1000>;
interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "i2c"; clock-names = "i2c";
clocks = <&cru PCLK_I2C0>; clocks = <&cru PCLK_I2C0>;
@ -458,6 +459,7 @@
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
arm,pl330-broken-no-flushp; arm,pl330-broken-no-flushp;
arm,pl330-periph-burst;
clocks = <&cru ACLK_DMAC>; clocks = <&cru ACLK_DMAC>;
clock-names = "apb_pclk"; clock-names = "apb_pclk";
#dma-cells = <1>; #dma-cells = <1>;

6
arch/arm/boot/dts/ti/omap/omap4-l4-abe.dtsi
View File

@ -109,6 +109,8 @@
reg = <0x0 0xff>, /* MPU private access */ reg = <0x0 0xff>, /* MPU private access */
<0x49022000 0xff>; /* L3 Interconnect */ <0x49022000 0xff>; /* L3 Interconnect */
reg-names = "mpu", "dma"; reg-names = "mpu", "dma";
clocks = <&abe_clkctrl OMAP4_MCBSP1_CLKCTRL 24>;
clock-names = "fck";
interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "common"; interrupt-names = "common";
ti,buffer-size = <128>; ti,buffer-size = <128>;
@ -142,6 +144,8 @@
reg = <0x0 0xff>, /* MPU private access */ reg = <0x0 0xff>, /* MPU private access */
<0x49024000 0xff>; /* L3 Interconnect */ <0x49024000 0xff>; /* L3 Interconnect */
reg-names = "mpu", "dma"; reg-names = "mpu", "dma";
clocks = <&abe_clkctrl OMAP4_MCBSP2_CLKCTRL 24>;
clock-names = "fck";
interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "common"; interrupt-names = "common";
ti,buffer-size = <128>; ti,buffer-size = <128>;
@ -175,6 +179,8 @@
reg = <0x0 0xff>, /* MPU private access */ reg = <0x0 0xff>, /* MPU private access */
<0x49026000 0xff>; /* L3 Interconnect */ <0x49026000 0xff>; /* L3 Interconnect */
reg-names = "mpu", "dma"; reg-names = "mpu", "dma";
clocks = <&abe_clkctrl OMAP4_MCBSP3_CLKCTRL 24>;
clock-names = "fck";
interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "common"; interrupt-names = "common";
ti,buffer-size = <128>; ti,buffer-size = <128>;

2
arch/arm/boot/dts/ti/omap/omap4-l4.dtsi
View File

@ -2043,6 +2043,8 @@
compatible = "ti,omap4-mcbsp"; compatible = "ti,omap4-mcbsp";
reg = <0x0 0xff>; /* L4 Interconnect */ reg = <0x0 0xff>; /* L4 Interconnect */
reg-names = "mpu"; reg-names = "mpu";
clocks = <&l4_per_clkctrl OMAP4_MCBSP4_CLKCTRL 24>;
clock-names = "fck";
interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "common"; interrupt-names = "common";
ti,buffer-size = <128>; ti,buffer-size = <128>;

6
arch/arm/boot/dts/ti/omap/omap5-l4-abe.dtsi
View File

@ -109,6 +109,8 @@
reg = <0x0 0xff>, /* MPU private access */ reg = <0x0 0xff>, /* MPU private access */
<0x49022000 0xff>; /* L3 Interconnect */ <0x49022000 0xff>; /* L3 Interconnect */
reg-names = "mpu", "dma"; reg-names = "mpu", "dma";
clocks = <&abe_clkctrl OMAP5_MCBSP1_CLKCTRL 24>;
clock-names = "fck";
interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "common"; interrupt-names = "common";
ti,buffer-size = <128>; ti,buffer-size = <128>;
@ -142,6 +144,8 @@
reg = <0x0 0xff>, /* MPU private access */ reg = <0x0 0xff>, /* MPU private access */
<0x49024000 0xff>; /* L3 Interconnect */ <0x49024000 0xff>; /* L3 Interconnect */
reg-names = "mpu", "dma"; reg-names = "mpu", "dma";
clocks = <&abe_clkctrl OMAP5_MCBSP2_CLKCTRL 24>;
clock-names = "fck";
interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "common"; interrupt-names = "common";
ti,buffer-size = <128>; ti,buffer-size = <128>;
@ -175,6 +179,8 @@
reg = <0x0 0xff>, /* MPU private access */ reg = <0x0 0xff>, /* MPU private access */
<0x49026000 0xff>; /* L3 Interconnect */ <0x49026000 0xff>; /* L3 Interconnect */
reg-names = "mpu", "dma"; reg-names = "mpu", "dma";
clocks = <&abe_clkctrl OMAP5_MCBSP3_CLKCTRL 24>;
clock-names = "fck";
interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "common"; interrupt-names = "common";
ti,buffer-size = <128>; ti,buffer-size = <128>;

60
arch/arm/mach-omap1/board-ams-delta.c
View File

@ -550,6 +550,7 @@ static struct platform_device *ams_delta_devices[] __initdata = {
&ams_delta_nand_device, &ams_delta_nand_device,
&ams_delta_lcd_device, &ams_delta_lcd_device,
&cx20442_codec_device, &cx20442_codec_device,
&modem_nreset_device,
}; };
static struct gpiod_lookup_table *ams_delta_gpio_tables[] __initdata = { static struct gpiod_lookup_table *ams_delta_gpio_tables[] __initdata = {
@ -782,26 +783,28 @@ static struct plat_serial8250_port ams_delta_modem_ports[] = {
{ }, { },
}; };
static int ams_delta_modem_pm_activate(struct device *dev)
{
modem_priv.regulator = regulator_get(dev, "RESET#");
if (IS_ERR(modem_priv.regulator))
return -EPROBE_DEFER;
return 0;
}
static struct dev_pm_domain ams_delta_modem_pm_domain = {
.activate = ams_delta_modem_pm_activate,
};
static struct platform_device ams_delta_modem_device = { static struct platform_device ams_delta_modem_device = {
.name = "serial8250", .name = "serial8250",
.id = PLAT8250_DEV_PLATFORM1, .id = PLAT8250_DEV_PLATFORM1,
.dev = { .dev = {
.platform_data = ams_delta_modem_ports, .platform_data = ams_delta_modem_ports,
.pm_domain = &ams_delta_modem_pm_domain,
}, },
}; };
static int __init modem_nreset_init(void)
{
int err;
err = platform_device_register(&modem_nreset_device);
if (err)
pr_err("Couldn't register the modem regulator device\n");
return err;
}
/* /*
* This function expects MODEM IRQ number already assigned to the port. * This function expects MODEM IRQ number already assigned to the port.
* The MODEM device requires its RESET# pin kept high during probe. * The MODEM device requires its RESET# pin kept high during probe.
@ -833,37 +836,6 @@ static int __init ams_delta_modem_init(void)
} }
arch_initcall_sync(ams_delta_modem_init); arch_initcall_sync(ams_delta_modem_init);
static int __init late_init(void)
{
int err;
err = modem_nreset_init();
if (err)
return err;
/*
* Once the modem device is registered, the modem_nreset
* regulator can be requested on behalf of that device.
*/
modem_priv.regulator = regulator_get(&ams_delta_modem_device.dev,
"RESET#");
if (IS_ERR(modem_priv.regulator)) {
err = PTR_ERR(modem_priv.regulator);
goto unregister;
}
return 0;
unregister:
platform_device_unregister(&ams_delta_modem_device);
return err;
}
static void __init ams_delta_init_late(void)
{
omap1_init_late();
late_init();
}
static void __init ams_delta_map_io(void) static void __init ams_delta_map_io(void)
{ {
omap1_map_io(); omap1_map_io();
@ -877,7 +849,7 @@ MACHINE_START(AMS_DELTA, "Amstrad E3 (Delta)")
.init_early = omap1_init_early, .init_early = omap1_init_early,
.init_irq = omap1_init_irq, .init_irq = omap1_init_irq,
.init_machine = ams_delta_init, .init_machine = ams_delta_init,
.init_late = ams_delta_init_late, .init_late = omap1_init_late,
.init_time = omap1_timer_init, .init_time = omap1_timer_init,
.restart = omap1_restart, .restart = omap1_restart,
MACHINE_END MACHINE_END

14
arch/arm/mach-omap1/timer32k.c
View File

@ -176,17 +176,18 @@ static u64 notrace omap_32k_read_sched_clock(void)
return sync32k_cnt_reg ? readl_relaxed(sync32k_cnt_reg) : 0; return sync32k_cnt_reg ? readl_relaxed(sync32k_cnt_reg) : 0;
} }
static struct timespec64 persistent_ts;
static cycles_t cycles;
static unsigned int persistent_mult, persistent_shift;
/** /**
* omap_read_persistent_clock64 - Return time from a persistent clock. * omap_read_persistent_clock64 - Return time from a persistent clock.
* @ts: &struct timespec64 for the returned time
* *
* Reads the time from a source which isn't disabled during PM, the * Reads the time from a source which isn't disabled during PM, the
* 32k sync timer. Convert the cycles elapsed since last read into * 32k sync timer. Convert the cycles elapsed since last read into
* nsecs and adds to a monotonically increasing timespec64. * nsecs and adds to a monotonically increasing timespec64.
*/ */
static struct timespec64 persistent_ts;
static cycles_t cycles;
static unsigned int persistent_mult, persistent_shift;
static void omap_read_persistent_clock64(struct timespec64 *ts) static void omap_read_persistent_clock64(struct timespec64 *ts)
{ {
unsigned long long nsecs; unsigned long long nsecs;
@ -206,10 +207,9 @@ static void omap_read_persistent_clock64(struct timespec64 *ts)
/** /**
* omap_init_clocksource_32k - setup and register counter 32k as a * omap_init_clocksource_32k - setup and register counter 32k as a
* kernel clocksource * kernel clocksource
* @pbase: base addr of counter_32k module * @vbase: base addr of counter_32k module
* @size: size of counter_32k to map
* *
* Returns 0 upon success or negative error code upon failure. * Returns: %0 upon success or negative error code upon failure.
* *
*/ */
static int __init omap_init_clocksource_32k(void __iomem *vbase) static int __init omap_init_clocksource_32k(void __iomem *vbase)

2
arch/arm/mach-omap2/omap_hwmod.c
View File

@ -2209,7 +2209,7 @@ int omap_hwmod_parse_module_range(struct omap_hwmod *oh,
return err; return err;
pr_debug("omap_hwmod: %s %pOFn at %pR\n", pr_debug("omap_hwmod: %s %pOFn at %pR\n",
oh->name, np, &res); oh->name, np, res);
if (oh && oh->mpu_rt_idx) { if (oh && oh->mpu_rt_idx) {
omap_hwmod_fix_mpu_rt_idx(oh, np, res); omap_hwmod_fix_mpu_rt_idx(oh, np, res);

32
arch/arm64/boot/dts/qcom/apq8096-db820c.dts
View File

@ -62,25 +62,23 @@
stdout-path = "serial0:115200n8"; stdout-path = "serial0:115200n8";
}; };
clocks { div1_mclk: divclk1 {
divclk4: divclk4 { compatible = "gpio-gate-clock";
compatible = "fixed-clock"; pinctrl-0 = <&audio_mclk>;
#clock-cells = <0>; pinctrl-names = "default";
clock-frequency = <32768>; clocks = <&rpmcc RPM_SMD_DIV_CLK1>;
clock-output-names = "divclk4"; #clock-cells = <0>;
enable-gpios = <&pm8994_gpios 15 0>;
};
pinctrl-names = "default"; divclk4: divclk4 {
pinctrl-0 = <&divclk4_pin_a>; compatible = "fixed-clock";
}; #clock-cells = <0>;
clock-frequency = <32768>;
clock-output-names = "divclk4";
div1_mclk: divclk1 { pinctrl-names = "default";
compatible = "gpio-gate-clock"; pinctrl-0 = <&divclk4_pin_a>;
pinctrl-0 = <&audio_mclk>;
pinctrl-names = "default";
clocks = <&rpmcc RPM_SMD_DIV_CLK1>;
#clock-cells = <0>;
enable-gpios = <&pm8994_gpios 15 0>;
};
}; };
gpio-keys { gpio-keys {

32
arch/arm64/boot/dts/qcom/msm8996-xiaomi-common.dtsi
View File

@ -11,26 +11,24 @@
#include <dt-bindings/pinctrl/qcom,pmic-gpio.h> #include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
/ { / {
clocks { divclk1_cdc: divclk1 {
divclk1_cdc: divclk1 { compatible = "gpio-gate-clock";
compatible = "gpio-gate-clock"; clocks = <&rpmcc RPM_SMD_DIV_CLK1>;
clocks = <&rpmcc RPM_SMD_DIV_CLK1>; #clock-cells = <0>;
#clock-cells = <0>; enable-gpios = <&pm8994_gpios 15 GPIO_ACTIVE_HIGH>;
enable-gpios = <&pm8994_gpios 15 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&divclk1_default>; pinctrl-0 = <&divclk1_default>;
}; };
divclk4: divclk4 { divclk4: divclk4 {
compatible = "fixed-clock"; compatible = "fixed-clock";
#clock-cells = <0>; #clock-cells = <0>;
clock-frequency = <32768>; clock-frequency = <32768>;
clock-output-names = "divclk4"; clock-output-names = "divclk4";
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&divclk4_pin_a>; pinctrl-0 = <&divclk4_pin_a>;
};
}; };
gpio-keys { gpio-keys {

16
arch/arm64/boot/dts/qcom/msm8996-xiaomi-gemini.dts
View File

@ -20,16 +20,14 @@
qcom,pmic-id = <0x20009 0x2000a 0x00 0x00>; qcom,pmic-id = <0x20009 0x2000a 0x00 0x00>;
qcom,board-id = <31 0>; qcom,board-id = <31 0>;
clocks { divclk2_haptics: divclk2 {
divclk2_haptics: divclk2 { compatible = "fixed-clock";
compatible = "fixed-clock"; #clock-cells = <0>;
#clock-cells = <0>; clock-frequency = <32768>;
clock-frequency = <32768>; clock-output-names = "divclk2";
clock-output-names = "divclk2";
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&divclk2_pin_a>; pinctrl-0 = <&divclk2_pin_a>;
};
}; };
}; };

2
arch/arm64/boot/dts/qcom/sa8775p-pmics.dtsi
View File

@ -173,7 +173,7 @@
compatible = "qcom,pmm8654au-gpio", "qcom,spmi-gpio"; compatible = "qcom,pmm8654au-gpio", "qcom,spmi-gpio";
reg = <0x8800>; reg = <0x8800>;
gpio-controller; gpio-controller;
gpio-ranges = <&pmm8654au_2_gpios 0 0 12>; gpio-ranges = <&pmm8654au_1_gpios 0 0 12>;
#gpio-cells = <2>; #gpio-cells = <2>;
interrupt-controller; interrupt-controller;
#interrupt-cells = <2>; #interrupt-cells = <2>;

10
arch/arm64/boot/dts/rockchip/px30-ringneck-haikou.dts
View File

@ -68,15 +68,17 @@
simple-audio-card,format = "i2s"; simple-audio-card,format = "i2s";
simple-audio-card,name = "Haikou,I2S-codec"; simple-audio-card,name = "Haikou,I2S-codec";
simple-audio-card,mclk-fs = <512>; simple-audio-card,mclk-fs = <512>;
simple-audio-card,frame-master = <&sgtl5000_codec>;
simple-audio-card,bitclock-master = <&sgtl5000_codec>;
simple-audio-card,codec { sgtl5000_codec: simple-audio-card,codec {
clocks = <&sgtl5000_clk>;
sound-dai = <&sgtl5000>; sound-dai = <&sgtl5000>;
// Prevent the dai subsystem from overwriting the clock
// frequency. We are using a fixed-frequency oscillator.
system-clock-fixed;
}; };
simple-audio-card,cpu { simple-audio-card,cpu {
bitclock-master;
frame-master;
sound-dai = <&i2s0_8ch>; sound-dai = <&i2s0_8ch>;
}; };
}; };

1
arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi
View File

@ -492,6 +492,7 @@
&i2s0 { &i2s0 {
pinctrl-0 = <&i2s0_2ch_bus>; pinctrl-0 = <&i2s0_2ch_bus>;
pinctrl-1 = <&i2s0_2ch_bus_bclk_off>;
rockchip,capture-channels = <2>; rockchip,capture-channels = <2>;
rockchip,playback-channels = <2>; rockchip,playback-channels = <2>;
status = "okay"; status = "okay";

10
arch/arm64/boot/dts/rockchip/rk3399.dtsi
View File

@ -2457,6 +2457,16 @@
<4 RK_PA0 1 &pcfg_pull_none>; <4 RK_PA0 1 &pcfg_pull_none>;
}; };
i2s0_2ch_bus_bclk_off: i2s0-2ch-bus-bclk-off {
rockchip,pins =
<3 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>,
<3 RK_PD1 1 &pcfg_pull_none>,
<3 RK_PD2 1 &pcfg_pull_none>,
<3 RK_PD3 1 &pcfg_pull_none>,
<3 RK_PD7 1 &pcfg_pull_none>,
<4 RK_PA0 1 &pcfg_pull_none>;
};
i2s0_8ch_bus: i2s0-8ch-bus { i2s0_8ch_bus: i2s0-8ch-bus {
rockchip,pins = rockchip,pins =
<3 RK_PD0 1 &pcfg_pull_none>, <3 RK_PD0 1 &pcfg_pull_none>,

3
arch/riscv/Kconfig
View File

@ -273,11 +273,9 @@ config RISCV_DMA_NONCOHERENT
select ARCH_HAS_SYNC_DMA_FOR_CPU select ARCH_HAS_SYNC_DMA_FOR_CPU
select ARCH_HAS_SYNC_DMA_FOR_DEVICE select ARCH_HAS_SYNC_DMA_FOR_DEVICE
select DMA_BOUNCE_UNALIGNED_KMALLOC if SWIOTLB select DMA_BOUNCE_UNALIGNED_KMALLOC if SWIOTLB
select DMA_DIRECT_REMAP if MMU
config RISCV_NONSTANDARD_CACHE_OPS config RISCV_NONSTANDARD_CACHE_OPS
bool bool
depends on RISCV_DMA_NONCOHERENT
help help
This enables function pointer support for non-standard noncoherent This enables function pointer support for non-standard noncoherent
systems to handle cache management. systems to handle cache management.
@ -550,6 +548,7 @@ config RISCV_ISA_ZICBOM
depends on RISCV_ALTERNATIVE depends on RISCV_ALTERNATIVE
default y default y
select RISCV_DMA_NONCOHERENT select RISCV_DMA_NONCOHERENT
select DMA_DIRECT_REMAP
help help
Adds support to dynamically detect the presence of the ZICBOM Adds support to dynamically detect the presence of the ZICBOM
extension (Cache Block Management Operations) and enable its extension (Cache Block Management Operations) and enable its

1
arch/riscv/Kconfig.errata
View File

@ -77,6 +77,7 @@ config ERRATA_THEAD_PBMT
config ERRATA_THEAD_CMO config ERRATA_THEAD_CMO
bool "Apply T-Head cache management errata" bool "Apply T-Head cache management errata"
depends on ERRATA_THEAD && MMU depends on ERRATA_THEAD && MMU
select DMA_DIRECT_REMAP
select RISCV_DMA_NONCOHERENT select RISCV_DMA_NONCOHERENT
default y default y
help help

2
arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
View File

@ -431,7 +431,7 @@
}; };
ss-pins { ss-pins {
pinmux = <GPIOMUX(48, GPOUT_SYS_SPI0_FSS, pinmux = <GPIOMUX(49, GPOUT_SYS_SPI0_FSS,
GPOEN_ENABLE, GPOEN_ENABLE,
GPI_SYS_SPI0_FSS)>; GPI_SYS_SPI0_FSS)>;
bias-disable; bias-disable;

1
arch/riscv/boot/dts/thead/th1520.dtsi
View File

@ -139,6 +139,7 @@
interrupt-parent = <&plic>; interrupt-parent = <&plic>;
#address-cells = <2>; #address-cells = <2>;
#size-cells = <2>; #size-cells = <2>;
dma-noncoherent;
ranges; ranges;
plic: interrupt-controller@ffd8000000 { plic: interrupt-controller@ffd8000000 {

2
drivers/cache/Kconfig vendored
View File

@ -3,7 +3,7 @@ menu "Cache Drivers"
config AX45MP_L2_CACHE config AX45MP_L2_CACHE
bool "Andes Technology AX45MP L2 Cache controller" bool "Andes Technology AX45MP L2 Cache controller"
depends on RISCV_DMA_NONCOHERENT depends on RISCV
select RISCV_NONSTANDARD_CACHE_OPS select RISCV_NONSTANDARD_CACHE_OPS
help help
Support for the L2 cache controller on Andes Technology AX45MP platforms. Support for the L2 cache controller on Andes Technology AX45MP platforms.

5
drivers/clk/ti/clk-44xx.c
View File

@ -749,9 +749,14 @@ static struct ti_dt_clk omap44xx_clks[] = {
DT_CLK(NULL, "mcbsp1_sync_mux_ck", "abe-clkctrl:0028:26"), DT_CLK(NULL, "mcbsp1_sync_mux_ck", "abe-clkctrl:0028:26"),
DT_CLK(NULL, "mcbsp2_sync_mux_ck", "abe-clkctrl:0030:26"), DT_CLK(NULL, "mcbsp2_sync_mux_ck", "abe-clkctrl:0030:26"),
DT_CLK(NULL, "mcbsp3_sync_mux_ck", "abe-clkctrl:0038:26"), DT_CLK(NULL, "mcbsp3_sync_mux_ck", "abe-clkctrl:0038:26"),
DT_CLK("40122000.mcbsp", "prcm_fck", "abe-clkctrl:0028:26"),
DT_CLK("40124000.mcbsp", "prcm_fck", "abe-clkctrl:0030:26"),
DT_CLK("40126000.mcbsp", "prcm_fck", "abe-clkctrl:0038:26"),
DT_CLK(NULL, "mcbsp4_sync_mux_ck", "l4-per-clkctrl:00c0:26"), DT_CLK(NULL, "mcbsp4_sync_mux_ck", "l4-per-clkctrl:00c0:26"),
DT_CLK("48096000.mcbsp", "prcm_fck", "l4-per-clkctrl:00c0:26"),
DT_CLK(NULL, "ocp2scp_usb_phy_phy_48m", "l3-init-clkctrl:00c0:8"), DT_CLK(NULL, "ocp2scp_usb_phy_phy_48m", "l3-init-clkctrl:00c0:8"),
DT_CLK(NULL, "otg_60m_gfclk", "l3-init-clkctrl:0040:24"), DT_CLK(NULL, "otg_60m_gfclk", "l3-init-clkctrl:0040:24"),
DT_CLK(NULL, "pad_fck", "pad_clks_ck"),
DT_CLK(NULL, "per_mcbsp4_gfclk", "l4-per-clkctrl:00c0:24"), DT_CLK(NULL, "per_mcbsp4_gfclk", "l4-per-clkctrl:00c0:24"),
DT_CLK(NULL, "pmd_stm_clock_mux_ck", "emu-sys-clkctrl:0000:20"), DT_CLK(NULL, "pmd_stm_clock_mux_ck", "emu-sys-clkctrl:0000:20"),
DT_CLK(NULL, "pmd_trace_clk_mux_ck", "emu-sys-clkctrl:0000:22"), DT_CLK(NULL, "pmd_trace_clk_mux_ck", "emu-sys-clkctrl:0000:22"),

4
drivers/clk/ti/clk-54xx.c
View File

@ -565,15 +565,19 @@ static struct ti_dt_clk omap54xx_clks[] = {
DT_CLK(NULL, "gpio8_dbclk", "l4per-clkctrl:00f8:8"), DT_CLK(NULL, "gpio8_dbclk", "l4per-clkctrl:00f8:8"),
DT_CLK(NULL, "mcbsp1_gfclk", "abe-clkctrl:0028:24"), DT_CLK(NULL, "mcbsp1_gfclk", "abe-clkctrl:0028:24"),
DT_CLK(NULL, "mcbsp1_sync_mux_ck", "abe-clkctrl:0028:26"), DT_CLK(NULL, "mcbsp1_sync_mux_ck", "abe-clkctrl:0028:26"),
DT_CLK("40122000.mcbsp", "prcm_fck", "abe-clkctrl:0028:26"),
DT_CLK(NULL, "mcbsp2_gfclk", "abe-clkctrl:0030:24"), DT_CLK(NULL, "mcbsp2_gfclk", "abe-clkctrl:0030:24"),
DT_CLK(NULL, "mcbsp2_sync_mux_ck", "abe-clkctrl:0030:26"), DT_CLK(NULL, "mcbsp2_sync_mux_ck", "abe-clkctrl:0030:26"),
DT_CLK("40124000.mcbsp", "prcm_fck", "abe-clkctrl:0030:26"),
DT_CLK(NULL, "mcbsp3_gfclk", "abe-clkctrl:0038:24"), DT_CLK(NULL, "mcbsp3_gfclk", "abe-clkctrl:0038:24"),
DT_CLK(NULL, "mcbsp3_sync_mux_ck", "abe-clkctrl:0038:26"), DT_CLK(NULL, "mcbsp3_sync_mux_ck", "abe-clkctrl:0038:26"),
DT_CLK("40126000.mcbsp", "prcm_fck", "abe-clkctrl:0038:26"),
DT_CLK(NULL, "mmc1_32khz_clk", "l3init-clkctrl:0008:8"), DT_CLK(NULL, "mmc1_32khz_clk", "l3init-clkctrl:0008:8"),
DT_CLK(NULL, "mmc1_fclk", "l3init-clkctrl:0008:25"), DT_CLK(NULL, "mmc1_fclk", "l3init-clkctrl:0008:25"),
DT_CLK(NULL, "mmc1_fclk_mux", "l3init-clkctrl:0008:24"), DT_CLK(NULL, "mmc1_fclk_mux", "l3init-clkctrl:0008:24"),
DT_CLK(NULL, "mmc2_fclk", "l3init-clkctrl:0010:25"), DT_CLK(NULL, "mmc2_fclk", "l3init-clkctrl:0010:25"),
DT_CLK(NULL, "mmc2_fclk_mux", "l3init-clkctrl:0010:24"), DT_CLK(NULL, "mmc2_fclk_mux", "l3init-clkctrl:0010:24"),
DT_CLK(NULL, "pad_fck", "pad_clks_ck"),
DT_CLK(NULL, "sata_ref_clk", "l3init-clkctrl:0068:8"), DT_CLK(NULL, "sata_ref_clk", "l3init-clkctrl:0068:8"),
DT_CLK(NULL, "timer10_gfclk_mux", "l4per-clkctrl:0008:24"), DT_CLK(NULL, "timer10_gfclk_mux", "l4per-clkctrl:0008:24"),
DT_CLK(NULL, "timer11_gfclk_mux", "l4per-clkctrl:0010:24"), DT_CLK(NULL, "timer11_gfclk_mux", "l4per-clkctrl:0010:24"),

2
drivers/firmware/imx/imx-dsp.c
View File

@ -114,11 +114,11 @@ static int imx_dsp_setup_channels(struct imx_dsp_ipc *dsp_ipc)
dsp_chan->idx = i % 2; dsp_chan->idx = i % 2;
dsp_chan->ch = mbox_request_channel_byname(cl, chan_name); dsp_chan->ch = mbox_request_channel_byname(cl, chan_name);
if (IS_ERR(dsp_chan->ch)) { if (IS_ERR(dsp_chan->ch)) {
kfree(dsp_chan->name);
ret = PTR_ERR(dsp_chan->ch); ret = PTR_ERR(dsp_chan->ch);
if (ret != -EPROBE_DEFER) if (ret != -EPROBE_DEFER)
dev_err(dev, "Failed to request mbox chan %s ret %d\n", dev_err(dev, "Failed to request mbox chan %s ret %d\n",
chan_name, ret); chan_name, ret);
kfree(dsp_chan->name);
goto out; goto out;
} }

10
drivers/soc/renesas/Kconfig
View File

@ -334,12 +334,14 @@ if RISCV
config ARCH_R9A07G043 config ARCH_R9A07G043
bool "RISC-V Platform support for RZ/Five" bool "RISC-V Platform support for RZ/Five"
depends on NONPORTABLE depends on NONPORTABLE
depends on RISCV_ALTERNATIVE
depends on !RISCV_ISA_ZICBOM
depends on RISCV_SBI
select ARCH_RZG2L select ARCH_RZG2L
select AX45MP_L2_CACHE if RISCV_DMA_NONCOHERENT select AX45MP_L2_CACHE
select DMA_GLOBAL_POOL select DMA_GLOBAL_POOL
select ERRATA_ANDES if RISCV_SBI select ERRATA_ANDES
select ERRATA_ANDES_CMO if ERRATA_ANDES select ERRATA_ANDES_CMO
help help
This enables support for the Renesas RZ/Five SoC. This enables support for the Renesas RZ/Five SoC.