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synced 2025-10-02 06:06:17 +10:00
drm/amdgpu: Cleanup amdgpu/amdgpu_cgs.c
Fixes the below: ERROR: switch and case should be at the same indent WARNING: Prefer 'unsigned int' to bare use of 'unsigned' WARNING: Block comments use * on subsequent lines WARNING: Comparisons should place the constant on the right side of the test Cc: Christian König <christian.koenig@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Srinivasan Shanmugam <srinivasan.shanmugam@amd.com> Reviewed-by: Guchun Chen <guchun.chen@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -41,13 +41,13 @@ struct amdgpu_cgs_device {
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((struct amdgpu_cgs_device *)cgs_device)->adev
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static uint32_t amdgpu_cgs_read_register(struct cgs_device *cgs_device, unsigned offset)
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static uint32_t amdgpu_cgs_read_register(struct cgs_device *cgs_device, unsigned int offset)
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{
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CGS_FUNC_ADEV;
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return RREG32(offset);
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}
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static void amdgpu_cgs_write_register(struct cgs_device *cgs_device, unsigned offset,
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static void amdgpu_cgs_write_register(struct cgs_device *cgs_device, unsigned int offset,
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uint32_t value)
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{
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CGS_FUNC_ADEV;
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@ -56,7 +56,7 @@ static void amdgpu_cgs_write_register(struct cgs_device *cgs_device, unsigned of
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static uint32_t amdgpu_cgs_read_ind_register(struct cgs_device *cgs_device,
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enum cgs_ind_reg space,
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unsigned index)
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unsigned int index)
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{
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CGS_FUNC_ADEV;
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switch (space) {
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@ -84,7 +84,7 @@ static uint32_t amdgpu_cgs_read_ind_register(struct cgs_device *cgs_device,
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static void amdgpu_cgs_write_ind_register(struct cgs_device *cgs_device,
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enum cgs_ind_reg space,
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unsigned index, uint32_t value)
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unsigned int index, uint32_t value)
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{
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CGS_FUNC_ADEV;
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switch (space) {
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@ -163,38 +163,38 @@ static uint16_t amdgpu_get_firmware_version(struct cgs_device *cgs_device,
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uint16_t fw_version = 0;
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switch (type) {
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case CGS_UCODE_ID_SDMA0:
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fw_version = adev->sdma.instance[0].fw_version;
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break;
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case CGS_UCODE_ID_SDMA1:
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fw_version = adev->sdma.instance[1].fw_version;
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break;
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case CGS_UCODE_ID_CP_CE:
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fw_version = adev->gfx.ce_fw_version;
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break;
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case CGS_UCODE_ID_CP_PFP:
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fw_version = adev->gfx.pfp_fw_version;
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break;
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case CGS_UCODE_ID_CP_ME:
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fw_version = adev->gfx.me_fw_version;
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break;
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case CGS_UCODE_ID_CP_MEC:
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fw_version = adev->gfx.mec_fw_version;
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break;
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case CGS_UCODE_ID_CP_MEC_JT1:
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fw_version = adev->gfx.mec_fw_version;
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break;
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case CGS_UCODE_ID_CP_MEC_JT2:
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fw_version = adev->gfx.mec_fw_version;
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break;
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case CGS_UCODE_ID_RLC_G:
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fw_version = adev->gfx.rlc_fw_version;
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break;
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case CGS_UCODE_ID_STORAGE:
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break;
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default:
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DRM_ERROR("firmware type %d do not have version\n", type);
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break;
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case CGS_UCODE_ID_SDMA0:
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fw_version = adev->sdma.instance[0].fw_version;
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break;
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case CGS_UCODE_ID_SDMA1:
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fw_version = adev->sdma.instance[1].fw_version;
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break;
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case CGS_UCODE_ID_CP_CE:
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fw_version = adev->gfx.ce_fw_version;
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break;
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case CGS_UCODE_ID_CP_PFP:
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fw_version = adev->gfx.pfp_fw_version;
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break;
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case CGS_UCODE_ID_CP_ME:
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fw_version = adev->gfx.me_fw_version;
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break;
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case CGS_UCODE_ID_CP_MEC:
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fw_version = adev->gfx.mec_fw_version;
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break;
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case CGS_UCODE_ID_CP_MEC_JT1:
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fw_version = adev->gfx.mec_fw_version;
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break;
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case CGS_UCODE_ID_CP_MEC_JT2:
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fw_version = adev->gfx.mec_fw_version;
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break;
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case CGS_UCODE_ID_RLC_G:
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fw_version = adev->gfx.rlc_fw_version;
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break;
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case CGS_UCODE_ID_STORAGE:
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break;
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default:
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DRM_ERROR("firmware type %d do not have version\n", type);
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break;
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}
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return fw_version;
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}
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@ -205,7 +205,7 @@ static int amdgpu_cgs_get_firmware_info(struct cgs_device *cgs_device,
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{
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CGS_FUNC_ADEV;
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if ((CGS_UCODE_ID_SMU != type) && (CGS_UCODE_ID_SMU_SK != type)) {
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if (type != CGS_UCODE_ID_SMU && type != CGS_UCODE_ID_SMU_SK) {
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uint64_t gpu_addr;
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uint32_t data_size;
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const struct gfx_firmware_header_v1_0 *header;
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@ -232,7 +232,7 @@ static int amdgpu_cgs_get_firmware_info(struct cgs_device *cgs_device,
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info->mc_addr = gpu_addr;
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info->version = (uint16_t)le32_to_cpu(header->header.ucode_version);
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if (CGS_UCODE_ID_CP_MEC == type)
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if (type == CGS_UCODE_ID_CP_MEC)
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info->image_size = le32_to_cpu(header->jt_offset) << 2;
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info->fw_version = amdgpu_get_firmware_version(cgs_device, type);
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