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[ARM] netwinder: clean up GPIO naming

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Netwinder was using gpio_xxx names which could clash with the GPIO
layer.  Add a 'nw_' prefix to ensure that these remain separate.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This commit is contained in:
Russell King 2008-12-06 08:25:16 +00:00 committed by Russell King
parent 7ec80ddf04
commit 70d13e083c
15 changed files with 64 additions and 62 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
arch/arm/mach-footbridge/cats-hw.c
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@ -10,6 +10,7 @@
#include <linux/init.h>
#include <linux/screen_info.h>
#include <linux/io.h>
#include <linux/spinlock.h>
#include <asm/hardware/dec21285.h>
#include <asm/mach-types.h>

1
arch/arm/mach-footbridge/common.c
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@ -14,6 +14,7 @@
#include <linux/list.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/spinlock.h>
#include <asm/pgtable.h>
#include <asm/page.h>

1
arch/arm/mach-footbridge/dc21285-timer.c
View File

@ -7,6 +7,7 @@
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/spinlock.h>
#include <asm/irq.h>

1
arch/arm/mach-footbridge/dc21285.c
View File

@ -17,6 +17,7 @@
#include <linux/ioport.h>
#include <linux/irq.h>
#include <linux/io.h>
#include <linux/spinlock.h>
#include <asm/irq.h>
#include <asm/system.h>

1
arch/arm/mach-footbridge/dma.c
View File

@ -12,6 +12,7 @@
*/
#include <linux/init.h>
#include <linux/io.h>
#include <linux/spinlock.h>
#include <asm/dma.h>
#include <asm/scatterlist.h>

1
arch/arm/mach-footbridge/ebsa285.c
View File

@ -4,6 +4,7 @@
* EBSA285 machine fixup
*/
#include <linux/init.h>
#include <linux/spinlock.h>
#include <asm/hardware/dec21285.h>
#include <asm/mach-types.h>

9
arch/arm/mach-footbridge/include/mach/hardware.h
View File

@ -86,10 +86,11 @@
#define CPLD_FLASH_WR_ENABLE 1
#ifndef __ASSEMBLY__
extern void gpio_modify_op(int mask, int set);
extern void gpio_modify_io(int mask, int in);
extern int gpio_read(void);
extern void cpld_modify(int mask, int set);
extern spinlock_t nw_gpio_lock;
extern void nw_gpio_modify_op(unsigned int mask, unsigned int set);
extern void nw_gpio_modify_io(unsigned int mask, unsigned int in);
extern unsigned int nw_gpio_read(void);
extern void nw_cpld_modify(unsigned int mask, unsigned int set);
#endif
#define pcibios_assign_all_busses() 1

1
arch/arm/mach-footbridge/isa-irq.c
View File

@ -19,6 +19,7 @@
#include <linux/list.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/spinlock.h>
#include <asm/mach/irq.h>

54
arch/arm/mach-footbridge/netwinder-hw.c
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@ -11,6 +11,7 @@
#include <linux/delay.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/spinlock.h>
#include <asm/hardware/dec21285.h>
#include <asm/leds.h>
@ -67,13 +68,14 @@ static inline void wb977_ww(int reg, int val)
/*
* This is a lock for accessing ports GP1_IO_BASE and GP2_IO_BASE
*/
DEFINE_SPINLOCK(gpio_lock);
DEFINE_SPINLOCK(nw_gpio_lock);
EXPORT_SYMBOL(nw_gpio_lock);
static unsigned int current_gpio_op;
static unsigned int current_gpio_io;
static unsigned int current_cpld;
void gpio_modify_op(int mask, int set)
void nw_gpio_modify_op(unsigned int mask, unsigned int set)
{
unsigned int new_gpio, changed;
@ -86,6 +88,7 @@ void gpio_modify_op(int mask, int set)
if (changed & 0xff00)
outb(new_gpio >> 8, GP2_IO_BASE);
}
EXPORT_SYMBOL(nw_gpio_modify_op);
static inline void __gpio_modify_io(int mask, int in)
{
@ -118,7 +121,7 @@ static inline void __gpio_modify_io(int mask, int in)
}
}
void gpio_modify_io(int mask, int in)
void nw_gpio_modify_io(unsigned int mask, unsigned int in)
{
/* Open up the SuperIO chip */
wb977_open();
@ -128,11 +131,13 @@ void gpio_modify_io(int mask, int in)
/* Close up the EFER gate */
wb977_close();
}
EXPORT_SYMBOL(nw_gpio_modify_io);
int gpio_read(void)
unsigned int nw_gpio_read(void)
{
return inb(GP1_IO_BASE) | inb(GP2_IO_BASE) << 8;
}
EXPORT_SYMBOL(nw_gpio_read);
/*
* Initialise the Winbond W83977F global registers
@ -322,9 +327,9 @@ static inline void wb977_init_gpio(void)
/*
* Set Group1/Group2 outputs
*/
spin_lock_irqsave(&gpio_lock, flags);
gpio_modify_op(-1, GPIO_RED_LED | GPIO_FAN);
spin_unlock_irqrestore(&gpio_lock, flags);
spin_lock_irqsave(&nw_gpio_lock, flags);
nw_gpio_modify_op(-1, GPIO_RED_LED | GPIO_FAN);
spin_unlock_irqrestore(&nw_gpio_lock, flags);
}
/*
@ -359,34 +364,35 @@ static void __init wb977_init(void)
wb977_close();
}
void cpld_modify(int mask, int set)
void nw_cpld_modify(unsigned int mask, unsigned int set)
{
int msk;
current_cpld = (current_cpld & ~mask) | set;
gpio_modify_io(GPIO_DATA | GPIO_IOCLK | GPIO_IOLOAD, 0);
gpio_modify_op(GPIO_IOLOAD, 0);
nw_gpio_modify_io(GPIO_DATA | GPIO_IOCLK | GPIO_IOLOAD, 0);
nw_gpio_modify_op(GPIO_IOLOAD, 0);
for (msk = 8; msk; msk >>= 1) {
int bit = current_cpld & msk;
gpio_modify_op(GPIO_DATA | GPIO_IOCLK, bit ? GPIO_DATA : 0);
gpio_modify_op(GPIO_IOCLK, GPIO_IOCLK);
nw_gpio_modify_op(GPIO_DATA | GPIO_IOCLK, bit ? GPIO_DATA : 0);
nw_gpio_modify_op(GPIO_IOCLK, GPIO_IOCLK);
}
gpio_modify_op(GPIO_IOCLK|GPIO_DATA, 0);
gpio_modify_op(GPIO_IOLOAD|GPIO_DSCLK, GPIO_IOLOAD|GPIO_DSCLK);
gpio_modify_op(GPIO_IOLOAD, 0);
nw_gpio_modify_op(GPIO_IOCLK|GPIO_DATA, 0);
nw_gpio_modify_op(GPIO_IOLOAD|GPIO_DSCLK, GPIO_IOLOAD|GPIO_DSCLK);
nw_gpio_modify_op(GPIO_IOLOAD, 0);
}
EXPORT_SYMBOL(nw_cpld_modify);
static void __init cpld_init(void)
{
unsigned long flags;
spin_lock_irqsave(&gpio_lock, flags);
cpld_modify(-1, CPLD_UNMUTE | CPLD_7111_DISABLE);
spin_unlock_irqrestore(&gpio_lock, flags);
spin_lock_irqsave(&nw_gpio_lock, flags);
nw_cpld_modify(-1, CPLD_UNMUTE | CPLD_7111_DISABLE);
spin_unlock_irqrestore(&nw_gpio_lock, flags);
}
static unsigned char rwa_unlock[] __initdata =
@ -596,12 +602,6 @@ static void __init rwa010_init(void)
rwa010_soundblaster_reset();
}
EXPORT_SYMBOL(gpio_lock);
EXPORT_SYMBOL(gpio_modify_op);
EXPORT_SYMBOL(gpio_modify_io);
EXPORT_SYMBOL(cpld_modify);
EXPORT_SYMBOL(gpio_read);
/*
* Initialise any other hardware after we've got the PCI bus
* initialised. We may need the PCI bus to talk to this other
@ -616,9 +616,9 @@ static int __init nw_hw_init(void)
cpld_init();
rwa010_init();
spin_lock_irqsave(&gpio_lock, flags);
gpio_modify_op(GPIO_RED_LED|GPIO_GREEN_LED, DEFAULT_LEDS);
spin_unlock_irqrestore(&gpio_lock, flags);
spin_lock_irqsave(&nw_gpio_lock, flags);
nw_gpio_modify_op(GPIO_RED_LED|GPIO_GREEN_LED, DEFAULT_LEDS);
spin_unlock_irqrestore(&nw_gpio_lock, flags);
}
return 0;
}

7
arch/arm/mach-footbridge/netwinder-leds.c
View File

@ -32,7 +32,6 @@ static char led_state;
static char hw_led_state;
static DEFINE_SPINLOCK(leds_lock);
extern spinlock_t gpio_lock;
static void netwinder_leds_event(led_event_t evt)
{
@ -121,9 +120,9 @@ static void netwinder_leds_event(led_event_t evt)
spin_unlock_irqrestore(&leds_lock, flags);
if (led_state & LED_STATE_ENABLED) {
spin_lock_irqsave(&gpio_lock, flags);
gpio_modify_op(GPIO_RED_LED | GPIO_GREEN_LED, hw_led_state);
spin_unlock_irqrestore(&gpio_lock, flags);
spin_lock_irqsave(&nw_gpio_lock, flags);
nw_gpio_modify_op(GPIO_RED_LED | GPIO_GREEN_LED, hw_led_state);
spin_unlock_irqrestore(&nw_gpio_lock, flags);
}
}

1
arch/arm/mach-footbridge/personal.c
View File

@ -4,6 +4,7 @@
* Personal server (Skiff) machine fixup
*/
#include <linux/init.h>
#include <linux/spinlock.h>
#include <asm/hardware/dec21285.h>
#include <asm/mach-types.h>

25
drivers/char/ds1620.c
View File

@ -43,52 +43,51 @@ static const char *fan_state[] = { "off", "on", "on (hardwired)" };
* chance that the WaveArtist driver could touch these bits to
* enable or disable the speaker.
*/
extern spinlock_t gpio_lock;
extern unsigned int system_rev;
static inline void netwinder_ds1620_set_clk(int clk)
{
gpio_modify_op(GPIO_DSCLK, clk ? GPIO_DSCLK : 0);
nw_gpio_modify_op(GPIO_DSCLK, clk ? GPIO_DSCLK : 0);
}
static inline void netwinder_ds1620_set_data(int dat)
{
gpio_modify_op(GPIO_DATA, dat ? GPIO_DATA : 0);
nw_gpio_modify_op(GPIO_DATA, dat ? GPIO_DATA : 0);
}
static inline int netwinder_ds1620_get_data(void)
{
return gpio_read() & GPIO_DATA;
return nw_gpio_read() & GPIO_DATA;
}
static inline void netwinder_ds1620_set_data_dir(int dir)
{
gpio_modify_io(GPIO_DATA, dir ? GPIO_DATA : 0);
nw_gpio_modify_io(GPIO_DATA, dir ? GPIO_DATA : 0);
}
static inline void netwinder_ds1620_reset(void)
{
cpld_modify(CPLD_DS_ENABLE, 0);
cpld_modify(CPLD_DS_ENABLE, CPLD_DS_ENABLE);
nw_cpld_modify(CPLD_DS_ENABLE, 0);
nw_cpld_modify(CPLD_DS_ENABLE, CPLD_DS_ENABLE);
}
static inline void netwinder_lock(unsigned long *flags)
{
spin_lock_irqsave(&gpio_lock, *flags);
spin_lock_irqsave(&nw_gpio_lock, *flags);
}
static inline void netwinder_unlock(unsigned long *flags)
{
spin_unlock_irqrestore(&gpio_lock, *flags);
spin_unlock_irqrestore(&nw_gpio_lock, *flags);
}
static inline void netwinder_set_fan(int i)
{
unsigned long flags;
spin_lock_irqsave(&gpio_lock, flags);
gpio_modify_op(GPIO_FAN, i ? GPIO_FAN : 0);
spin_unlock_irqrestore(&gpio_lock, flags);
spin_lock_irqsave(&nw_gpio_lock, flags);
nw_gpio_modify_op(GPIO_FAN, i ? GPIO_FAN : 0);
spin_unlock_irqrestore(&nw_gpio_lock, flags);
}
static inline int netwinder_get_fan(void)
@ -96,7 +95,7 @@ static inline int netwinder_get_fan(void)
if ((system_rev & 0xf000) == 0x4000)
return FAN_ALWAYS_ON;
return (gpio_read() & GPIO_FAN) ? FAN_ON : FAN_OFF;
return (nw_gpio_read() & GPIO_FAN) ? FAN_ON : FAN_OFF;
}
/*

8
drivers/char/nwflash.c
View File

@ -58,8 +58,6 @@ static volatile unsigned char *FLASH_BASE;
static int gbFlashSize = KFLASH_SIZE;
static DEFINE_MUTEX(nwflash_mutex);
extern spinlock_t gpio_lock;
static int get_flash_id(void)
{
volatile unsigned int c1, c2;
@ -616,9 +614,9 @@ static void kick_open(void)
* we want to write a bit pattern XXX1 to Xilinx to enable
* the write gate, which will be open for about the next 2ms.
*/
spin_lock_irqsave(&gpio_lock, flags);
cpld_modify(1, 1);
spin_unlock_irqrestore(&gpio_lock, flags);
spin_lock_irqsave(&nw_gpio_lock, flags);
nw_cpld_modify(CPLD_FLASH_WR_ENABLE, CPLD_FLASH_WR_ENABLE);
spin_unlock_irqrestore(&nw_gpio_lock, flags);
/*
* let the ISA bus to catch on...

7
drivers/mtd/maps/dc21285.c
View File

@ -32,16 +32,15 @@ static struct mtd_info *dc21285_mtd;
*/
static void nw_en_write(void)
{
extern spinlock_t gpio_lock;
unsigned long flags;
/*
* we want to write a bit pattern XXX1 to Xilinx to enable
* the write gate, which will be open for about the next 2ms.
*/
spin_lock_irqsave(&gpio_lock, flags);
cpld_modify(1, 1);
spin_unlock_irqrestore(&gpio_lock, flags);
spin_lock_irqsave(&nw_gpio_lock, flags);
nw_cpld_modify(CPLD_FLASH_WR_ENABLE, CPLD_FLASH_WR_ENABLE);
spin_unlock_irqrestore(&nw_gpio_lock, flags);
/*
* let the ISA bus to catch on...

8
sound/oss/waveartist.c
View File

@ -1483,16 +1483,14 @@ static void __exit unload_waveartist(struct address_info *hw)
#define VNC_HANDSET_DETECT 0x40
#define VNC_DISABLE_AUTOSWITCH 0x80
extern spinlock_t gpio_lock;
static inline void
vnc_mute_spkr(wavnc_info *devc)
{
unsigned long flags;
spin_lock_irqsave(&gpio_lock, flags);
cpld_modify(CPLD_UNMUTE, devc->spkr_mute_state ? 0 : CPLD_UNMUTE);
spin_unlock_irqrestore(&gpio_lock, flags);
spin_lock_irqsave(&nw_gpio_lock, flags);
nw_cpld_modify(CPLD_UNMUTE, devc->spkr_mute_state ? 0 : CPLD_UNMUTE);
spin_unlock_irqrestore(&nw_gpio_lock, flags);
}
static void