Stefan Agner c72c553249 ARM: imx: clk-vf610: define PLL's clock tree ... So far, the required PLL's (PLL1/PLL2/PLL5) have been initialized by boot loader and the kernel code defined fixed rates according to those default configurations. Beginning with the USB PLL7 the code started to initialize the PLL's itself (using imx_clk_pllv3). However, since commit dc4805c2e7 (ARM: imx: remove ENABLE and BYPASS bits from clk-pllv3 driver) imx_clk_pllv3 no longer takes care of the ENABLE and BYPASS bits, hence the USB PLL were not configured correctly anymore. This patch not only fixes those USB PLL's, but also makes use of the imx_clk_pllv3 for all PLL's and alignes the code with the PLL support of the i.MX6 series. Signed-off-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>		2014-11-04 13:40:14 +08:00
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clk
clock	ARM: imx: clk-vf610: define PLL's clock tree	2014-11-04 13:40:14 +08:00
dma
gpio
input	Input: drv260x - add TI drv260x haptics driver	2014-08-19 22:19:28 -07:00
interrupt-controller
mfd
phy
pinctrl	pinctrl: at91: add drive strength configuration	2014-09-05 10:32:06 +02:00
pwm
reset
reset-controller
soc
sound	ASoC: cs35l32: Add support for CS35L32 Boosted Amplifier	2014-08-16 17:03:22 -05:00
spmi
thermal