Jisheng Zhang 2bf847db0c riscv: extable: add type and data fields ... This is a riscv port of commit d6e2cc5647 ("arm64: extable: add `type` and `data` fields"). Signed-off-by: Jisheng Zhang <jszhang@kernel.org> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>		2022-01-05 17:52:54 -08:00
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asm	riscv: extable: add type and data fields	2022-01-05 17:52:54 -08:00
uapi/asm	ARM:	2021-11-02 11:24:14 -07:00