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			279 lines
		
	
	
		
			7.1 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
			
		
		
	
	
			279 lines
		
	
	
		
			7.1 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
/*
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 *    Disk Array driver for Compaq SMART2 Controllers
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 *    Copyright 1998 Compaq Computer Corporation
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 *
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 *    This program is free software; you can redistribute it and/or modify
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 *    it under the terms of the GNU General Public License as published by
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 *    the Free Software Foundation; either version 2 of the License, or
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 *    (at your option) any later version.
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 *
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 *    This program is distributed in the hope that it will be useful,
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 *    but WITHOUT ANY WARRANTY; without even the implied warranty of
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 *    MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
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 *    NON INFRINGEMENT.  See the GNU General Public License for more details.
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 *
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 *    You should have received a copy of the GNU General Public License
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 *    along with this program; if not, write to the Free Software
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 *    Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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 *
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 *    Questions/Comments/Bugfixes to iss_storagedev@hp.com
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 *
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 *    If you want to make changes, improve or add functionality to this
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 *    driver, you'll probably need the Compaq Array Controller Interface
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 *    Specificiation (Document number ECG086/1198)
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 */
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/*
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 * This file contains the controller communication implementation for
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 * Compaq SMART-1 and SMART-2 controllers.  To the best of my knowledge,
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 * this should support:
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 *
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 *  PCI:
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 *  SMART-2/P, SMART-2DH, SMART-2SL, SMART-221, SMART-3100ES, SMART-3200
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 *  Integerated SMART Array Controller, SMART-4200, SMART-4250ES
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 *
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 *  EISA:
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 *  SMART-2/E, SMART, IAES, IDA-2, IDA
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 */
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/*
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 * Memory mapped FIFO interface (SMART 42xx cards)
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 */
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static void smart4_submit_command(ctlr_info_t *h, cmdlist_t *c)
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{
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        writel(c->busaddr, h->vaddr + S42XX_REQUEST_PORT_OFFSET);
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}
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/*  
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 *  This card is the opposite of the other cards.  
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 *   0 turns interrupts on... 
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 *   0x08 turns them off... 
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 */
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static void smart4_intr_mask(ctlr_info_t *h, unsigned long val)
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{
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	if (val) 
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	{ /* Turn interrupts on */
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		writel(0, h->vaddr + S42XX_REPLY_INTR_MASK_OFFSET);
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	} else /* Turn them off */
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	{
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        	writel( S42XX_INTR_OFF, 
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			h->vaddr + S42XX_REPLY_INTR_MASK_OFFSET);
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	}
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}
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/*
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 *  For older cards FIFO Full = 0. 
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 *  On this card 0 means there is room, anything else FIFO Full. 
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 * 
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 */ 
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static unsigned long smart4_fifo_full(ctlr_info_t *h)
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{
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        return (!readl(h->vaddr + S42XX_REQUEST_PORT_OFFSET));
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}
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/* This type of controller returns -1 if the fifo is empty, 
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 *    Not 0 like the others.
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 *    And we need to let it know we read a value out 
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 */ 
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static unsigned long smart4_completed(ctlr_info_t *h)
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{
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	long register_value 
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		= readl(h->vaddr + S42XX_REPLY_PORT_OFFSET);
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	/* Fifo is empty */
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	if( register_value == 0xffffffff)
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		return 0; 	
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	/* Need to let it know we got the reply */
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	/* We do this by writing a 0 to the port we just read from */
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	writel(0, h->vaddr + S42XX_REPLY_PORT_OFFSET);
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	return ((unsigned long) register_value); 
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}
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 /*
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 *  This hardware returns interrupt pending at a different place and 
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 *  it does not tell us if the fifo is empty, we will have check  
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 *  that by getting a 0 back from the command_completed call. 
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 */
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static unsigned long smart4_intr_pending(ctlr_info_t *h)
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{
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	unsigned long register_value  = 
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		readl(h->vaddr + S42XX_INTR_STATUS);
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	if( register_value &  S42XX_INTR_PENDING) 
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		return  FIFO_NOT_EMPTY;	
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	return 0 ;
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}
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static struct access_method smart4_access = {
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	smart4_submit_command,
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	smart4_intr_mask,
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	smart4_fifo_full,
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	smart4_intr_pending,
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	smart4_completed,
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};
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/*
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 * Memory mapped FIFO interface (PCI SMART2 and SMART 3xxx cards)
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 */
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static void smart2_submit_command(ctlr_info_t *h, cmdlist_t *c)
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{
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	writel(c->busaddr, h->vaddr + COMMAND_FIFO);
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}
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static void smart2_intr_mask(ctlr_info_t *h, unsigned long val)
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{
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	writel(val, h->vaddr + INTR_MASK);
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}
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static unsigned long smart2_fifo_full(ctlr_info_t *h)
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{
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	return readl(h->vaddr + COMMAND_FIFO);
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}
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static unsigned long smart2_completed(ctlr_info_t *h)
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{
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	return readl(h->vaddr + COMMAND_COMPLETE_FIFO);
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}
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static unsigned long smart2_intr_pending(ctlr_info_t *h)
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{
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	return readl(h->vaddr + INTR_PENDING);
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}
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static struct access_method smart2_access = {
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	smart2_submit_command,
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	smart2_intr_mask,
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	smart2_fifo_full,
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	smart2_intr_pending,
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	smart2_completed,
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};
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/*
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 *  IO access for SMART-2/E cards
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 */
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static void smart2e_submit_command(ctlr_info_t *h, cmdlist_t *c)
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{
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	outl(c->busaddr, h->io_mem_addr + COMMAND_FIFO);
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}
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static void smart2e_intr_mask(ctlr_info_t *h, unsigned long val)
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{
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	outl(val, h->io_mem_addr + INTR_MASK);
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}
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static unsigned long smart2e_fifo_full(ctlr_info_t *h)
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{
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	return inl(h->io_mem_addr + COMMAND_FIFO);
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}
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static unsigned long smart2e_completed(ctlr_info_t *h)
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{
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	return inl(h->io_mem_addr + COMMAND_COMPLETE_FIFO);
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}
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static unsigned long smart2e_intr_pending(ctlr_info_t *h)
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{
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	return inl(h->io_mem_addr + INTR_PENDING);
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}
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static struct access_method smart2e_access = {
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	smart2e_submit_command,
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	smart2e_intr_mask,
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	smart2e_fifo_full,
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	smart2e_intr_pending,
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	smart2e_completed,
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};
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/*
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 *  IO access for older SMART-1 type cards
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 */
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#define SMART1_SYSTEM_MASK		0xC8E
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#define SMART1_SYSTEM_DOORBELL		0xC8F
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#define SMART1_LOCAL_MASK		0xC8C
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#define SMART1_LOCAL_DOORBELL		0xC8D
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#define SMART1_INTR_MASK		0xC89
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#define SMART1_LISTADDR			0xC90
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#define SMART1_LISTLEN			0xC94
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#define SMART1_TAG			0xC97
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#define SMART1_COMPLETE_ADDR		0xC98
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#define SMART1_LISTSTATUS		0xC9E
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#define CHANNEL_BUSY			0x01
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#define CHANNEL_CLEAR			0x02
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static void smart1_submit_command(ctlr_info_t *h, cmdlist_t *c)
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{
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	/*
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	 * This __u16 is actually a bunch of control flags on SMART
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	 * and below.  We want them all to be zero.
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	 */
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	c->hdr.size = 0;
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	outb(CHANNEL_CLEAR, h->io_mem_addr + SMART1_SYSTEM_DOORBELL);
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	outl(c->busaddr, h->io_mem_addr + SMART1_LISTADDR);
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	outw(c->size, h->io_mem_addr + SMART1_LISTLEN);
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	outb(CHANNEL_BUSY, h->io_mem_addr + SMART1_LOCAL_DOORBELL);
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}
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static void smart1_intr_mask(ctlr_info_t *h, unsigned long val)
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{
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	if (val == 1) {
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		outb(0xFD, h->io_mem_addr + SMART1_SYSTEM_DOORBELL);
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		outb(CHANNEL_BUSY, h->io_mem_addr + SMART1_LOCAL_DOORBELL);
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		outb(0x01, h->io_mem_addr + SMART1_INTR_MASK);
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		outb(0x01, h->io_mem_addr + SMART1_SYSTEM_MASK);
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	} else {
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		outb(0, h->io_mem_addr + 0xC8E);
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	}
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}
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static unsigned long smart1_fifo_full(ctlr_info_t *h)
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{
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	unsigned char chan;
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	chan = inb(h->io_mem_addr + SMART1_SYSTEM_DOORBELL) & CHANNEL_CLEAR;
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	return chan;
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}
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static unsigned long smart1_completed(ctlr_info_t *h)
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{
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	unsigned char status;
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	unsigned long cmd;
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	if (inb(h->io_mem_addr + SMART1_SYSTEM_DOORBELL) & CHANNEL_BUSY) {
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		outb(CHANNEL_BUSY, h->io_mem_addr + SMART1_SYSTEM_DOORBELL);
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		cmd = inl(h->io_mem_addr + SMART1_COMPLETE_ADDR);
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		status = inb(h->io_mem_addr + SMART1_LISTSTATUS);
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		outb(CHANNEL_CLEAR, h->io_mem_addr + SMART1_LOCAL_DOORBELL);
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		/*
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		 * this is x86 (actually compaq x86) only, so it's ok
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		 */
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		if (cmd) ((cmdlist_t*)bus_to_virt(cmd))->req.hdr.rcode = status;
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	} else {
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		cmd = 0;
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	}
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	return cmd;
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}
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static unsigned long smart1_intr_pending(ctlr_info_t *h)
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{
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	unsigned char chan;
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	chan = inb(h->io_mem_addr + SMART1_SYSTEM_DOORBELL) & CHANNEL_BUSY;
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	return chan;
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}
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static struct access_method smart1_access = {
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	smart1_submit_command,
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	smart1_intr_mask,
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	smart1_fifo_full,
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	smart1_intr_pending,
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	smart1_completed,
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};
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