Andre Przywara a3eebcb61f dts: add riscv include prefix link ... The Allwinner D1/D1s SoCs (with a RISC-V core) use an (almost?) identical die as their R528/T113-s siblings with ARM Cortex-A7 cores. To allow sharing the basic SoC .dtsi files across those two architectures as well, introduce a symlink to the RISC-V DT directory. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Acked-by: Palmer Dabbelt <palmer@rivosinc.com> Link: https://lore.kernel.org/r/20230320005249.13403-2-andre.przywara@arm.com Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>		2023-03-27 22:45:22 +02:00
..
include-prefixes	dts: add riscv include prefix link	2023-03-27 22:45:22 +02:00
libfdt
.gitignore
checks.c
data.c
dt_to_config
dt-extract-compatibles
dtc-lexer.l
dtc-parser.y
dtc.c
dtc.h
dtx_diff
fdtget.c
fdtoverlay.c
fdtput.c
flattree.c
fstree.c
livetree.c
Makefile
of_unittest_expect	of: add processing of EXPECT_NOT to of_unittest_expect	2023-02-17 15:46:20 -06:00
srcpos.c
srcpos.h
treesource.c
update-dtc-source.sh
util.c
util.h
version_gen.h
yamltree.c