mirror of
https://kernel.googlesource.com/pub/scm/linux/kernel/git/stable/linux-stable.git
synced 2025-09-27 17:32:00 +10:00
Merge branches 'clk-parent', 'clk-renesas', 'clk-mediatek' and 'clk-cleanup' into clk-next
* clk-parent: clk: check for disabled clock-provider in of_clk_get_hw_from_clkspec() * clk-renesas: (24 commits) clk: renesas: r9a09g047: Add clock and reset signals for the TSU IP clk: renesas: rzv2h: Adjust for CPG_BUS_m_MSTOP starting from m = 1 clk: renesas: r7s9210: Distinguish clocks by clock type clk: renesas: rzg2l: Remove unneeded nullify checks clk: renesas: cpg-mssr: Remove obsolete nullify check clk: renesas: r9a09g057: Add entries for the DMACs clk: renesas: r9a09g047: Add CANFD clocks and resets clk: renesas: r9a09g047: Add CRU0 clocks and resets clk: renesas: rzv2h: Update error message clk: renesas: rzg2l: Update error message clk: renesas: r9a09g047: Add ICU clock/reset clk: renesas: r9a07g043: Fix HP clock source for RZ/Five clk: renesas: r9a09g047: Add SDHI clocks/resets clk: renesas: r8a779h0: Add VSPX clock clk: renesas: r8a779h0: Add FCPVX clock clk: renesas: r8a08g045: Check the source of the CPU PLL settings clk: renesas: r9a09g047: Add WDT clocks and resets clk: renesas: r8a779h0: Add ISP core clocks clk: renesas: r8a779g0: Add ISP core clocks clk: renesas: r8a779a0: Add ISP core clocks ... * clk-mediatek: clk: mediatek: Add SMI LARBs reset for MT8188 dt-bindings: clock: mediatek: Add SMI LARBs reset for MT8188 clk: mediatek: mt8188-vdo1: Add VDO1_DPI1_HDMI clock for hdmitx dt-bindings: clock: mediatek,mt8188: Add VDO1_DPI1_HDMI clock * clk-cleanup: dt-bindings: clocks: atmel,at91rm9200-pmc: add missing compatibles clk: davinci: remove support for da830 dt-bindings: clock: ti: Convert ti-clkctrl.txt to json-schema clk: mmp: Fix NULL vs IS_ERR() check clk: Print an error when clk registration fails clk: Correct the data types of the variables in clk_calc_new_rates clk: imgtec: use %pe for better readability of errors while printing clk: stm32f4: fix an uninitialized variable clk: keystone: syscon-clk: Do not use syscon helper to build regmap
This commit is contained in:
Stephen Boyd
commit
316f4b91f9
@ -34,6 +34,8 @@ properties:
|
||||
- enum:
|
||||
- atmel,at91rm9200-pmc
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||||
- atmel,at91sam9260-pmc
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||||
- atmel,at91sam9261-pmc
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||||
- atmel,at91sam9263-pmc
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||||
- atmel,at91sam9g45-pmc
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||||
- atmel,at91sam9n12-pmc
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||||
- atmel,at91sam9rl-pmc
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||||
@ -111,6 +113,8 @@ allOf:
|
||||
enum:
|
||||
- atmel,at91rm9200-pmc
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||||
- atmel,at91sam9260-pmc
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||||
- atmel,at91sam9261-pmc
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||||
- atmel,at91sam9263-pmc
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- atmel,at91sam9g20-pmc
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then:
|
||||
properties:
|
||||
|
||||
@ -57,6 +57,27 @@ required:
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||||
- reg
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||||
- '#clock-cells'
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allOf:
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- if:
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properties:
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compatible:
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contains:
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enum:
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- mediatek,mt8188-camsys-rawa
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||||
- mediatek,mt8188-camsys-rawb
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- mediatek,mt8188-camsys-yuva
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- mediatek,mt8188-camsys-yuvb
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- mediatek,mt8188-imgsys-wpe1
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- mediatek,mt8188-imgsys-wpe2
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- mediatek,mt8188-imgsys-wpe3
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- mediatek,mt8188-imgsys1-dip-nr
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- mediatek,mt8188-imgsys1-dip-top
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- mediatek,mt8188-ipesys
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|
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then:
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required:
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- '#reset-cells'
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additionalProperties: false
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||||
|
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examples:
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|
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65
Documentation/devicetree/bindings/clock/ti,clkctrl.yaml
Normal file
65
Documentation/devicetree/bindings/clock/ti,clkctrl.yaml
Normal file
@ -0,0 +1,65 @@
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# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/ti,clkctrl.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Texas Instruments clkctrl clock
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maintainers:
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- Tony Lindgren <tony@atomide.com>
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- Andreas Kemnade <andreas@kemnade.info>
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description: |
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Texas Instruments SoCs can have a clkctrl clock controller for each
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interconnect target module. The clkctrl clock controller manages functional
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and interface clocks for each module. Each clkctrl controller can also
|
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gate one or more optional functional clocks for a module, and can have one
|
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or more clock muxes. There is a clkctrl clock controller typically for each
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||||
interconnect target module on omap4 and later variants.
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||||
|
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The clock consumers can specify the index of the clkctrl clock using
|
||||
the hardware offset from the clkctrl instance register space. The optional
|
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clocks can be specified by clkctrl hardware offset and the index of the
|
||||
optional clock.
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||||
|
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properties:
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||||
compatible:
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enum:
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- ti,clkctrl
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- ti,clkctrl-l4-cfg
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- ti,clkctrl-l4-per
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- ti,clkctrl-l4-secure
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- ti,clkctrl-l4-wkup
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||||
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"#clock-cells":
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const: 2
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|
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clock-output-names:
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maxItems: 1
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||||
|
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reg:
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||||
minItems: 1
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||||
maxItems: 8 # arbitrary, should be enough
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||||
|
||||
required:
|
||||
- compatible
|
||||
- "#clock-cells"
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||||
- clock-output-names
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||||
- reg
|
||||
|
||||
additionalProperties: false
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||||
|
||||
examples:
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||||
- |
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||||
bus {
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#address-cells = <1>;
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#size-cells = <1>;
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clock@20 {
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compatible = "ti,clkctrl";
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clock-output-names = "l4_per";
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reg = <0x20 0x1b0>;
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#clock-cells = <2>;
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};
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};
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@ -1,63 +0,0 @@
|
||||
Texas Instruments clkctrl clock binding
|
||||
|
||||
Texas Instruments SoCs can have a clkctrl clock controller for each
|
||||
interconnect target module. The clkctrl clock controller manages functional
|
||||
and interface clocks for each module. Each clkctrl controller can also
|
||||
gate one or more optional functional clocks for a module, and can have one
|
||||
or more clock muxes. There is a clkctrl clock controller typically for each
|
||||
interconnect target module on omap4 and later variants.
|
||||
|
||||
The clock consumers can specify the index of the clkctrl clock using
|
||||
the hardware offset from the clkctrl instance register space. The optional
|
||||
clocks can be specified by clkctrl hardware offset and the index of the
|
||||
optional clock.
|
||||
|
||||
For more information, please see the Linux clock framework binding at
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||||
Documentation/devicetree/bindings/clock/clock-bindings.txt.
|
||||
|
||||
Required properties :
|
||||
- compatible : shall be "ti,clkctrl" or a clock domain specific name:
|
||||
"ti,clkctrl-l4-cfg"
|
||||
"ti,clkctrl-l4-per"
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"ti,clkctrl-l4-secure"
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"ti,clkctrl-l4-wkup"
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- clock-output-names : from common clock binding
|
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- #clock-cells : shall contain 2 with the first entry being the instance
|
||||
offset from the clock domain base and the second being the
|
||||
clock index
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- reg : clock registers
|
||||
|
||||
Example: Clock controller node on omap 4430:
|
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&cm2 {
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l4per: cm@1400 {
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cm_l4per@0 {
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cm_l4per_clkctrl: clock@20 {
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compatible = "ti,clkctrl";
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clock-output-names = "l4_per";
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reg = <0x20 0x1b0>;
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#clock-cells = <2>;
|
||||
};
|
||||
};
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};
|
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};
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Example: Preprocessor helper macros in dt-bindings/clock/ti-clkctrl.h
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#define OMAP4_CLKCTRL_OFFSET 0x20
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#define OMAP4_CLKCTRL_INDEX(offset) ((offset) - OMAP4_CLKCTRL_OFFSET)
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#define MODULEMODE_HWCTRL 1
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#define MODULEMODE_SWCTRL 2
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#define OMAP4_GPTIMER10_CLKTRL OMAP4_CLKCTRL_INDEX(0x28)
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#define OMAP4_GPTIMER11_CLKTRL OMAP4_CLKCTRL_INDEX(0x30)
|
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#define OMAP4_GPTIMER2_CLKTRL OMAP4_CLKCTRL_INDEX(0x38)
|
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...
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#define OMAP4_GPIO2_CLKCTRL OMAP_CLKCTRL_INDEX(0x60)
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|
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Example: Clock consumer node for GPIO2:
|
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&gpio2 {
|
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clocks = <&cm_l4per_clkctrl OMAP4_GPIO2_CLKCTRL 0
|
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&cm_l4per_clkctrl OMAP4_GPIO2_CLKCTRL 8>;
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};
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@ -888,7 +888,6 @@ static int __init stm32f4_pll_ssc_parse_dt(struct device_node *np,
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struct stm32f4_pll_ssc *conf)
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{
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int ret;
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const char *s;
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if (!conf)
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return -EINVAL;
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@ -916,7 +915,8 @@ static int __init stm32f4_pll_ssc_parse_dt(struct device_node *np,
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conf->mod_type = ret;
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pr_debug("%pOF: SSCG settings: mod_freq: %d, mod_depth: %d mod_method: %s [%d]\n",
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np, conf->mod_freq, conf->mod_depth, s, conf->mod_type);
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np, conf->mod_freq, conf->mod_depth,
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stm32f4_ssc_mod_methods[ret], conf->mod_type);
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return 0;
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}
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@ -2283,7 +2283,7 @@ static struct clk_core *clk_calc_new_rates(struct clk_core *core,
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unsigned long min_rate;
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unsigned long max_rate;
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int p_index = 0;
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long ret;
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||||
int ret;
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||||
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||||
/* sanity */
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||||
if (IS_ERR_OR_NULL(core))
|
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@ -4397,6 +4397,13 @@ fail_ops:
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fail_name:
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||||
kref_put(&core->ref, __clk_release);
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fail_out:
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||||
if (dev) {
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dev_err_probe(dev, ret, "failed to register clk '%s' (%pS)\n",
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init->name, hw);
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} else {
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pr_err("%pOF: error %pe: failed to register clk '%s' (%pS)\n",
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np, ERR_PTR(ret), init->name, hw);
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}
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return ERR_PTR(ret);
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}
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@ -4,10 +4,8 @@ ifeq ($(CONFIG_COMMON_CLK), y)
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obj-$(CONFIG_ARCH_DAVINCI_DA8XX) += da8xx-cfgchip.o
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obj-y += pll.o
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obj-$(CONFIG_ARCH_DAVINCI_DA830) += pll-da830.o
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obj-$(CONFIG_ARCH_DAVINCI_DA850) += pll-da850.o
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obj-y += psc.o
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obj-$(CONFIG_ARCH_DAVINCI_DA830) += psc-da830.o
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obj-$(CONFIG_ARCH_DAVINCI_DA850) += psc-da850.o
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endif
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@ -1,71 +0,0 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
|
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* PLL clock descriptions for TI DA830/OMAP-L137/AM17XX
|
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*
|
||||
* Copyright (C) 2018 David Lechner <david@lechnology.com>
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*/
|
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#include <linux/clkdev.h>
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#include <linux/clk/davinci.h>
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#include <linux/bitops.h>
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#include <linux/init.h>
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#include <linux/types.h>
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#include "pll.h"
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static const struct davinci_pll_clk_info da830_pll_info = {
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.name = "pll0",
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.pllm_mask = GENMASK(4, 0),
|
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.pllm_min = 4,
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.pllm_max = 32,
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.pllout_min_rate = 300000000,
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.pllout_max_rate = 600000000,
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.flags = PLL_HAS_CLKMODE | PLL_HAS_PREDIV | PLL_HAS_POSTDIV,
|
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};
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|
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/*
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* NB: Technically, the clocks flagged as SYSCLK_FIXED_DIV are "fixed ratio",
|
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* meaning that we could change the divider as long as we keep the correct
|
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* ratio between all of the clocks, but we don't support that because there is
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* currently not a need for it.
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*/
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SYSCLK(2, pll0_sysclk2, pll0_pllen, 5, SYSCLK_FIXED_DIV);
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SYSCLK(3, pll0_sysclk3, pll0_pllen, 5, 0);
|
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SYSCLK(4, pll0_sysclk4, pll0_pllen, 5, SYSCLK_FIXED_DIV);
|
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SYSCLK(5, pll0_sysclk5, pll0_pllen, 5, 0);
|
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SYSCLK(6, pll0_sysclk6, pll0_pllen, 5, SYSCLK_FIXED_DIV);
|
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SYSCLK(7, pll0_sysclk7, pll0_pllen, 5, 0);
|
||||
|
||||
int da830_pll_init(struct device *dev, void __iomem *base, struct regmap *cfgchip)
|
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{
|
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struct clk *clk;
|
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|
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davinci_pll_clk_register(dev, &da830_pll_info, "ref_clk", base, cfgchip);
|
||||
|
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clk = davinci_pll_sysclk_register(dev, &pll0_sysclk2, base);
|
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clk_register_clkdev(clk, "pll0_sysclk2", "da830-psc0");
|
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clk_register_clkdev(clk, "pll0_sysclk2", "da830-psc1");
|
||||
|
||||
clk = davinci_pll_sysclk_register(dev, &pll0_sysclk3, base);
|
||||
clk_register_clkdev(clk, "pll0_sysclk3", "da830-psc0");
|
||||
|
||||
clk = davinci_pll_sysclk_register(dev, &pll0_sysclk4, base);
|
||||
clk_register_clkdev(clk, "pll0_sysclk4", "da830-psc0");
|
||||
clk_register_clkdev(clk, "pll0_sysclk4", "da830-psc1");
|
||||
|
||||
clk = davinci_pll_sysclk_register(dev, &pll0_sysclk5, base);
|
||||
clk_register_clkdev(clk, "pll0_sysclk5", "da830-psc1");
|
||||
|
||||
clk = davinci_pll_sysclk_register(dev, &pll0_sysclk6, base);
|
||||
clk_register_clkdev(clk, "pll0_sysclk6", "da830-psc0");
|
||||
|
||||
clk = davinci_pll_sysclk_register(dev, &pll0_sysclk7, base);
|
||||
|
||||
clk = davinci_pll_auxclk_register(dev, "pll0_auxclk", base);
|
||||
clk_register_clkdev(clk, NULL, "i2c_davinci.1");
|
||||
clk_register_clkdev(clk, "timer0", NULL);
|
||||
clk_register_clkdev(clk, NULL, "davinci-wdt");
|
||||
|
||||
return 0;
|
||||
}
|
||||
@ -840,25 +840,16 @@ int of_davinci_pll_init(struct device *dev, struct device_node *node,
|
||||
}
|
||||
|
||||
/* needed in early boot for clocksource/clockevent */
|
||||
#ifdef CONFIG_ARCH_DAVINCI_DA850
|
||||
CLK_OF_DECLARE(da850_pll0, "ti,da850-pll0", of_da850_pll0_init);
|
||||
#endif
|
||||
|
||||
static const struct of_device_id davinci_pll_of_match[] = {
|
||||
#ifdef CONFIG_ARCH_DAVINCI_DA850
|
||||
{ .compatible = "ti,da850-pll1", .data = of_da850_pll1_init },
|
||||
#endif
|
||||
{ }
|
||||
};
|
||||
|
||||
static const struct platform_device_id davinci_pll_id_table[] = {
|
||||
#ifdef CONFIG_ARCH_DAVINCI_DA830
|
||||
{ .name = "da830-pll", .driver_data = (kernel_ulong_t)da830_pll_init },
|
||||
#endif
|
||||
#ifdef CONFIG_ARCH_DAVINCI_DA850
|
||||
{ .name = "da850-pll0", .driver_data = (kernel_ulong_t)da850_pll0_init },
|
||||
{ .name = "da850-pll1", .driver_data = (kernel_ulong_t)da850_pll1_init },
|
||||
#endif
|
||||
{ }
|
||||
};
|
||||
|
||||
|
||||
@ -1,118 +0,0 @@
|
||||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* PSC clock descriptions for TI DA830/OMAP-L137/AM17XX
|
||||
*
|
||||
* Copyright (C) 2018 David Lechner <david@lechnology.com>
|
||||
*/
|
||||
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/clk.h>
|
||||
#include <linux/clkdev.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/types.h>
|
||||
|
||||
#include "psc.h"
|
||||
|
||||
LPSC_CLKDEV1(aemif_clkdev, NULL, "ti-aemif");
|
||||
LPSC_CLKDEV1(spi0_clkdev, NULL, "spi_davinci.0");
|
||||
LPSC_CLKDEV1(mmcsd_clkdev, NULL, "da830-mmc.0");
|
||||
LPSC_CLKDEV1(uart0_clkdev, NULL, "serial8250.0");
|
||||
|
||||
static const struct davinci_lpsc_clk_info da830_psc0_info[] = {
|
||||
LPSC(0, 0, tpcc, pll0_sysclk2, NULL, LPSC_ALWAYS_ENABLED),
|
||||
LPSC(1, 0, tptc0, pll0_sysclk2, NULL, LPSC_ALWAYS_ENABLED),
|
||||
LPSC(2, 0, tptc1, pll0_sysclk2, NULL, LPSC_ALWAYS_ENABLED),
|
||||
LPSC(3, 0, aemif, pll0_sysclk3, aemif_clkdev, LPSC_ALWAYS_ENABLED),
|
||||
LPSC(4, 0, spi0, pll0_sysclk2, spi0_clkdev, 0),
|
||||
LPSC(5, 0, mmcsd, pll0_sysclk2, mmcsd_clkdev, 0),
|
||||
LPSC(6, 0, aintc, pll0_sysclk4, NULL, LPSC_ALWAYS_ENABLED),
|
||||
LPSC(7, 0, arm_rom, pll0_sysclk2, NULL, LPSC_ALWAYS_ENABLED),
|
||||
LPSC(8, 0, secu_mgr, pll0_sysclk4, NULL, LPSC_ALWAYS_ENABLED),
|
||||
LPSC(9, 0, uart0, pll0_sysclk2, uart0_clkdev, 0),
|
||||
LPSC(10, 0, scr0_ss, pll0_sysclk2, NULL, LPSC_ALWAYS_ENABLED),
|
||||
LPSC(11, 0, scr1_ss, pll0_sysclk2, NULL, LPSC_ALWAYS_ENABLED),
|
||||
LPSC(12, 0, scr2_ss, pll0_sysclk2, NULL, LPSC_ALWAYS_ENABLED),
|
||||
LPSC(13, 0, pruss, pll0_sysclk2, NULL, LPSC_ALWAYS_ENABLED),
|
||||
LPSC(14, 0, arm, pll0_sysclk6, NULL, LPSC_ALWAYS_ENABLED),
|
||||
{ }
|
||||
};
|
||||
|
||||
static int da830_psc0_init(struct device *dev, void __iomem *base)
|
||||
{
|
||||
return davinci_psc_register_clocks(dev, da830_psc0_info, 16, base);
|
||||
}
|
||||
|
||||
static struct clk_bulk_data da830_psc0_parent_clks[] = {
|
||||
{ .id = "pll0_sysclk2" },
|
||||
{ .id = "pll0_sysclk3" },
|
||||
{ .id = "pll0_sysclk4" },
|
||||
{ .id = "pll0_sysclk6" },
|
||||
};
|
||||
|
||||
const struct davinci_psc_init_data da830_psc0_init_data = {
|
||||
.parent_clks = da830_psc0_parent_clks,
|
||||
.num_parent_clks = ARRAY_SIZE(da830_psc0_parent_clks),
|
||||
.psc_init = &da830_psc0_init,
|
||||
};
|
||||
|
||||
LPSC_CLKDEV3(usb0_clkdev, "fck", "da830-usb-phy-clks",
|
||||
NULL, "musb-da8xx",
|
||||
NULL, "cppi41-dmaengine");
|
||||
LPSC_CLKDEV1(usb1_clkdev, NULL, "ohci-da8xx");
|
||||
/* REVISIT: gpio-davinci.c should be modified to drop con_id */
|
||||
LPSC_CLKDEV1(gpio_clkdev, "gpio", NULL);
|
||||
LPSC_CLKDEV2(emac_clkdev, NULL, "davinci_emac.1",
|
||||
"fck", "davinci_mdio.0");
|
||||
LPSC_CLKDEV1(mcasp0_clkdev, NULL, "davinci-mcasp.0");
|
||||
LPSC_CLKDEV1(mcasp1_clkdev, NULL, "davinci-mcasp.1");
|
||||
LPSC_CLKDEV1(mcasp2_clkdev, NULL, "davinci-mcasp.2");
|
||||
LPSC_CLKDEV1(spi1_clkdev, NULL, "spi_davinci.1");
|
||||
LPSC_CLKDEV1(i2c1_clkdev, NULL, "i2c_davinci.2");
|
||||
LPSC_CLKDEV1(uart1_clkdev, NULL, "serial8250.1");
|
||||
LPSC_CLKDEV1(uart2_clkdev, NULL, "serial8250.2");
|
||||
LPSC_CLKDEV1(lcdc_clkdev, "fck", "da8xx_lcdc.0");
|
||||
LPSC_CLKDEV2(pwm_clkdev, "fck", "ehrpwm.0",
|
||||
"fck", "ehrpwm.1");
|
||||
LPSC_CLKDEV3(ecap_clkdev, "fck", "ecap.0",
|
||||
"fck", "ecap.1",
|
||||
"fck", "ecap.2");
|
||||
LPSC_CLKDEV2(eqep_clkdev, NULL, "eqep.0",
|
||||
NULL, "eqep.1");
|
||||
|
||||
static const struct davinci_lpsc_clk_info da830_psc1_info[] = {
|
||||
LPSC(1, 0, usb0, pll0_sysclk2, usb0_clkdev, 0),
|
||||
LPSC(2, 0, usb1, pll0_sysclk4, usb1_clkdev, 0),
|
||||
LPSC(3, 0, gpio, pll0_sysclk4, gpio_clkdev, 0),
|
||||
LPSC(5, 0, emac, pll0_sysclk4, emac_clkdev, 0),
|
||||
LPSC(6, 0, emif3, pll0_sysclk5, NULL, LPSC_ALWAYS_ENABLED),
|
||||
LPSC(7, 0, mcasp0, pll0_sysclk2, mcasp0_clkdev, 0),
|
||||
LPSC(8, 0, mcasp1, pll0_sysclk2, mcasp1_clkdev, 0),
|
||||
LPSC(9, 0, mcasp2, pll0_sysclk2, mcasp2_clkdev, 0),
|
||||
LPSC(10, 0, spi1, pll0_sysclk2, spi1_clkdev, 0),
|
||||
LPSC(11, 0, i2c1, pll0_sysclk4, i2c1_clkdev, 0),
|
||||
LPSC(12, 0, uart1, pll0_sysclk2, uart1_clkdev, 0),
|
||||
LPSC(13, 0, uart2, pll0_sysclk2, uart2_clkdev, 0),
|
||||
LPSC(16, 0, lcdc, pll0_sysclk2, lcdc_clkdev, 0),
|
||||
LPSC(17, 0, pwm, pll0_sysclk2, pwm_clkdev, 0),
|
||||
LPSC(20, 0, ecap, pll0_sysclk2, ecap_clkdev, 0),
|
||||
LPSC(21, 0, eqep, pll0_sysclk2, eqep_clkdev, 0),
|
||||
{ }
|
||||
};
|
||||
|
||||
static int da830_psc1_init(struct device *dev, void __iomem *base)
|
||||
{
|
||||
return davinci_psc_register_clocks(dev, da830_psc1_info, 32, base);
|
||||
}
|
||||
|
||||
static struct clk_bulk_data da830_psc1_parent_clks[] = {
|
||||
{ .id = "pll0_sysclk2" },
|
||||
{ .id = "pll0_sysclk4" },
|
||||
{ .id = "pll0_sysclk5" },
|
||||
};
|
||||
|
||||
const struct davinci_psc_init_data da830_psc1_init_data = {
|
||||
.parent_clks = da830_psc1_parent_clks,
|
||||
.num_parent_clks = ARRAY_SIZE(da830_psc1_parent_clks),
|
||||
.psc_init = &da830_psc1_init,
|
||||
};
|
||||
@ -494,22 +494,14 @@ int of_davinci_psc_clk_init(struct device *dev,
|
||||
}
|
||||
|
||||
static const struct of_device_id davinci_psc_of_match[] = {
|
||||
#ifdef CONFIG_ARCH_DAVINCI_DA850
|
||||
{ .compatible = "ti,da850-psc0", .data = &of_da850_psc0_init_data },
|
||||
{ .compatible = "ti,da850-psc1", .data = &of_da850_psc1_init_data },
|
||||
#endif
|
||||
{ }
|
||||
};
|
||||
|
||||
static const struct platform_device_id davinci_psc_id_table[] = {
|
||||
#ifdef CONFIG_ARCH_DAVINCI_DA830
|
||||
{ .name = "da830-psc0", .driver_data = (kernel_ulong_t)&da830_psc0_init_data },
|
||||
{ .name = "da830-psc1", .driver_data = (kernel_ulong_t)&da830_psc1_init_data },
|
||||
#endif
|
||||
#ifdef CONFIG_ARCH_DAVINCI_DA850
|
||||
{ .name = "da850-psc0", .driver_data = (kernel_ulong_t)&da850_psc0_init_data },
|
||||
{ .name = "da850-psc1", .driver_data = (kernel_ulong_t)&da850_psc1_init_data },
|
||||
#endif
|
||||
{ }
|
||||
};
|
||||
|
||||
|
||||
@ -94,14 +94,9 @@ struct davinci_psc_init_data {
|
||||
int (*psc_init)(struct device *dev, void __iomem *base);
|
||||
};
|
||||
|
||||
#ifdef CONFIG_ARCH_DAVINCI_DA830
|
||||
extern const struct davinci_psc_init_data da830_psc0_init_data;
|
||||
extern const struct davinci_psc_init_data da830_psc1_init_data;
|
||||
#endif
|
||||
#ifdef CONFIG_ARCH_DAVINCI_DA850
|
||||
extern const struct davinci_psc_init_data da850_psc0_init_data;
|
||||
extern const struct davinci_psc_init_data da850_psc1_init_data;
|
||||
extern const struct davinci_psc_init_data of_da850_psc0_init_data;
|
||||
extern const struct davinci_psc_init_data of_da850_psc1_init_data;
|
||||
#endif
|
||||
|
||||
#endif /* __CLK_DAVINCI_PSC_H__ */
|
||||
|
||||
@ -67,21 +67,21 @@ static void __init clk_boston_setup(struct device_node *np)
|
||||
|
||||
hw = clk_hw_register_fixed_rate(NULL, "input", NULL, 0, in_freq);
|
||||
if (IS_ERR(hw)) {
|
||||
pr_err("failed to register input clock: %ld\n", PTR_ERR(hw));
|
||||
pr_err("failed to register input clock: %pe\n", hw);
|
||||
goto fail_input;
|
||||
}
|
||||
onecell->hws[BOSTON_CLK_INPUT] = hw;
|
||||
|
||||
hw = clk_hw_register_fixed_rate(NULL, "sys", "input", 0, sys_freq);
|
||||
if (IS_ERR(hw)) {
|
||||
pr_err("failed to register sys clock: %ld\n", PTR_ERR(hw));
|
||||
pr_err("failed to register sys clock: %pe\n", hw);
|
||||
goto fail_sys;
|
||||
}
|
||||
onecell->hws[BOSTON_CLK_SYS] = hw;
|
||||
|
||||
hw = clk_hw_register_fixed_rate(NULL, "cpu", "input", 0, cpu_freq);
|
||||
if (IS_ERR(hw)) {
|
||||
pr_err("failed to register cpu clock: %ld\n", PTR_ERR(hw));
|
||||
pr_err("failed to register cpu clock: %pe\n", hw);
|
||||
goto fail_cpu;
|
||||
}
|
||||
onecell->hws[BOSTON_CLK_CPU] = hw;
|
||||
|
||||
@ -105,6 +105,12 @@ static struct clk_hw
|
||||
return &priv->hw;
|
||||
}
|
||||
|
||||
static const struct regmap_config ti_syscon_regmap_cfg = {
|
||||
.reg_bits = 32,
|
||||
.val_bits = 32,
|
||||
.reg_stride = 4,
|
||||
};
|
||||
|
||||
static int ti_syscon_gate_clk_probe(struct platform_device *pdev)
|
||||
{
|
||||
const struct ti_syscon_gate_clk_data *data, *p;
|
||||
@ -113,12 +119,17 @@ static int ti_syscon_gate_clk_probe(struct platform_device *pdev)
|
||||
int num_clks, num_parents, i;
|
||||
const char *parent_name;
|
||||
struct regmap *regmap;
|
||||
void __iomem *base;
|
||||
|
||||
data = device_get_match_data(dev);
|
||||
if (!data)
|
||||
return -EINVAL;
|
||||
|
||||
regmap = device_node_to_regmap(dev->of_node);
|
||||
base = devm_platform_ioremap_resource(pdev, 0);
|
||||
if (IS_ERR(base))
|
||||
return PTR_ERR(base);
|
||||
|
||||
regmap = regmap_init_mmio(dev, base, &ti_syscon_regmap_cfg);
|
||||
if (IS_ERR(regmap))
|
||||
return dev_err_probe(dev, PTR_ERR(regmap),
|
||||
"failed to get regmap\n");
|
||||
|
||||
@ -20,6 +20,8 @@ static const struct mtk_gate_regs cam_cg_regs = {
|
||||
#define GATE_CAM(_id, _name, _parent, _shift) \
|
||||
GATE_MTK(_id, _name, _parent, &cam_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
|
||||
|
||||
#define CAM_SYS_SMI_LARB_RST_OFF (0xA0)
|
||||
|
||||
static const struct mtk_gate cam_main_clks[] = {
|
||||
GATE_CAM(CLK_CAM_MAIN_LARB13, "cam_main_larb13", "top_cam", 0),
|
||||
GATE_CAM(CLK_CAM_MAIN_LARB14, "cam_main_larb14", "top_cam", 1),
|
||||
@ -72,6 +74,17 @@ static const struct mtk_gate cam_yuvb_clks[] = {
|
||||
GATE_CAM(CLK_CAM_YUVB_CAMTG, "cam_yuvb_camtg", "top_cam", 2),
|
||||
};
|
||||
|
||||
/* Reset for SMI larb 16a/16b/17a/17b */
|
||||
static u16 cam_sys_rst_ofs[] = {
|
||||
CAM_SYS_SMI_LARB_RST_OFF,
|
||||
};
|
||||
|
||||
static const struct mtk_clk_rst_desc cam_sys_rst_desc = {
|
||||
.version = MTK_RST_SIMPLE,
|
||||
.rst_bank_ofs = cam_sys_rst_ofs,
|
||||
.rst_bank_nr = ARRAY_SIZE(cam_sys_rst_ofs),
|
||||
};
|
||||
|
||||
static const struct mtk_clk_desc cam_main_desc = {
|
||||
.clks = cam_main_clks,
|
||||
.num_clks = ARRAY_SIZE(cam_main_clks),
|
||||
@ -80,21 +93,25 @@ static const struct mtk_clk_desc cam_main_desc = {
|
||||
static const struct mtk_clk_desc cam_rawa_desc = {
|
||||
.clks = cam_rawa_clks,
|
||||
.num_clks = ARRAY_SIZE(cam_rawa_clks),
|
||||
.rst_desc = &cam_sys_rst_desc,
|
||||
};
|
||||
|
||||
static const struct mtk_clk_desc cam_rawb_desc = {
|
||||
.clks = cam_rawb_clks,
|
||||
.num_clks = ARRAY_SIZE(cam_rawb_clks),
|
||||
.rst_desc = &cam_sys_rst_desc,
|
||||
};
|
||||
|
||||
static const struct mtk_clk_desc cam_yuva_desc = {
|
||||
.clks = cam_yuva_clks,
|
||||
.num_clks = ARRAY_SIZE(cam_yuva_clks),
|
||||
.rst_desc = &cam_sys_rst_desc,
|
||||
};
|
||||
|
||||
static const struct mtk_clk_desc cam_yuvb_desc = {
|
||||
.clks = cam_yuvb_clks,
|
||||
.num_clks = ARRAY_SIZE(cam_yuvb_clks),
|
||||
.rst_desc = &cam_sys_rst_desc,
|
||||
};
|
||||
|
||||
static const struct of_device_id of_match_clk_mt8188_cam[] = {
|
||||
|
||||
@ -20,6 +20,8 @@ static const struct mtk_gate_regs imgsys_cg_regs = {
|
||||
#define GATE_IMGSYS(_id, _name, _parent, _shift) \
|
||||
GATE_MTK(_id, _name, _parent, &imgsys_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
|
||||
|
||||
#define IMG_SYS_SMI_LARB_RST_OFF (0xC)
|
||||
|
||||
static const struct mtk_gate imgsys_main_clks[] = {
|
||||
GATE_IMGSYS(CLK_IMGSYS_MAIN_LARB9, "imgsys_main_larb9", "top_img", 0),
|
||||
GATE_IMGSYS(CLK_IMGSYS_MAIN_TRAW0, "imgsys_main_traw0", "top_img", 1),
|
||||
@ -58,6 +60,17 @@ static const struct mtk_gate imgsys1_dip_nr_clks[] = {
|
||||
GATE_IMGSYS(CLK_IMGSYS1_DIP_NR_DIP_NR, "imgsys1_dip_nr_dip_nr", "top_img", 1),
|
||||
};
|
||||
|
||||
/* Reset for SMI larb 10/11a/11b/11c/15 */
|
||||
static u16 img_sys_rst_ofs[] = {
|
||||
IMG_SYS_SMI_LARB_RST_OFF,
|
||||
};
|
||||
|
||||
static const struct mtk_clk_rst_desc img_sys_rst_desc = {
|
||||
.version = MTK_RST_SIMPLE,
|
||||
.rst_bank_ofs = img_sys_rst_ofs,
|
||||
.rst_bank_nr = ARRAY_SIZE(img_sys_rst_ofs),
|
||||
};
|
||||
|
||||
static const struct mtk_clk_desc imgsys_main_desc = {
|
||||
.clks = imgsys_main_clks,
|
||||
.num_clks = ARRAY_SIZE(imgsys_main_clks),
|
||||
@ -66,26 +79,31 @@ static const struct mtk_clk_desc imgsys_main_desc = {
|
||||
static const struct mtk_clk_desc imgsys_wpe1_desc = {
|
||||
.clks = imgsys_wpe1_clks,
|
||||
.num_clks = ARRAY_SIZE(imgsys_wpe1_clks),
|
||||
.rst_desc = &img_sys_rst_desc,
|
||||
};
|
||||
|
||||
static const struct mtk_clk_desc imgsys_wpe2_desc = {
|
||||
.clks = imgsys_wpe2_clks,
|
||||
.num_clks = ARRAY_SIZE(imgsys_wpe2_clks),
|
||||
.rst_desc = &img_sys_rst_desc,
|
||||
};
|
||||
|
||||
static const struct mtk_clk_desc imgsys_wpe3_desc = {
|
||||
.clks = imgsys_wpe3_clks,
|
||||
.num_clks = ARRAY_SIZE(imgsys_wpe3_clks),
|
||||
.rst_desc = &img_sys_rst_desc,
|
||||
};
|
||||
|
||||
static const struct mtk_clk_desc imgsys1_dip_top_desc = {
|
||||
.clks = imgsys1_dip_top_clks,
|
||||
.num_clks = ARRAY_SIZE(imgsys1_dip_top_clks),
|
||||
.rst_desc = &img_sys_rst_desc,
|
||||
};
|
||||
|
||||
static const struct mtk_clk_desc imgsys1_dip_nr_desc = {
|
||||
.clks = imgsys1_dip_nr_clks,
|
||||
.num_clks = ARRAY_SIZE(imgsys1_dip_nr_clks),
|
||||
.rst_desc = &img_sys_rst_desc,
|
||||
};
|
||||
|
||||
static const struct of_device_id of_match_clk_mt8188_imgsys_main[] = {
|
||||
|
||||
@ -20,6 +20,8 @@ static const struct mtk_gate_regs ipe_cg_regs = {
|
||||
#define GATE_IPE(_id, _name, _parent, _shift) \
|
||||
GATE_MTK(_id, _name, _parent, &ipe_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
|
||||
|
||||
#define IPE_SYS_SMI_LARB_RST_OFF (0xC)
|
||||
|
||||
static const struct mtk_gate ipe_clks[] = {
|
||||
GATE_IPE(CLK_IPE_DPE, "ipe_dpe", "top_ipe", 0),
|
||||
GATE_IPE(CLK_IPE_FDVT, "ipe_fdvt", "top_ipe", 1),
|
||||
@ -28,9 +30,21 @@ static const struct mtk_gate ipe_clks[] = {
|
||||
GATE_IPE(CLK_IPE_SMI_LARB12, "ipe_smi_larb12", "top_ipe", 4),
|
||||
};
|
||||
|
||||
/* Reset for SMI larb 12 */
|
||||
static u16 ipe_sys_rst_ofs[] = {
|
||||
IPE_SYS_SMI_LARB_RST_OFF,
|
||||
};
|
||||
|
||||
static const struct mtk_clk_rst_desc ipe_sys_rst_desc = {
|
||||
.version = MTK_RST_SIMPLE,
|
||||
.rst_bank_ofs = ipe_sys_rst_ofs,
|
||||
.rst_bank_nr = ARRAY_SIZE(ipe_sys_rst_ofs),
|
||||
};
|
||||
|
||||
static const struct mtk_clk_desc ipe_desc = {
|
||||
.clks = ipe_clks,
|
||||
.num_clks = ARRAY_SIZE(ipe_clks),
|
||||
.rst_desc = &ipe_sys_rst_desc,
|
||||
};
|
||||
|
||||
static const struct of_device_id of_match_clk_mt8188_ipe[] = {
|
||||
|
||||
@ -43,6 +43,12 @@ static const struct mtk_gate_regs vdo1_4_cg_regs = {
|
||||
.sta_ofs = 0x140,
|
||||
};
|
||||
|
||||
static const struct mtk_gate_regs vdo1_5_cg_regs = {
|
||||
.set_ofs = 0x400,
|
||||
.clr_ofs = 0x400,
|
||||
.sta_ofs = 0x400,
|
||||
};
|
||||
|
||||
#define GATE_VDO1_0(_id, _name, _parent, _shift) \
|
||||
GATE_MTK(_id, _name, _parent, &vdo1_0_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
|
||||
|
||||
@ -62,6 +68,9 @@ static const struct mtk_gate_regs vdo1_4_cg_regs = {
|
||||
#define GATE_VDO1_4(_id, _name, _parent, _shift) \
|
||||
GATE_MTK(_id, _name, _parent, &vdo1_4_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
|
||||
|
||||
#define GATE_VDO1_5(_id, _name, _parent, _shift) \
|
||||
GATE_MTK(_id, _name, _parent, &vdo1_5_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
|
||||
|
||||
static const struct mtk_gate vdo1_clks[] = {
|
||||
/* VDO1_0 */
|
||||
GATE_VDO1_0(CLK_VDO1_SMI_LARB2, "vdo1_smi_larb2", "top_vpp", 0),
|
||||
@ -129,6 +138,8 @@ static const struct mtk_gate vdo1_clks[] = {
|
||||
GATE_VDO1_3(CLK_VDO1_DISP_MONITOR_DPINTF, "vdo1_disp_monitor_dpintf_ck", "top_vpp", 17),
|
||||
/* VDO1_4 */
|
||||
GATE_VDO1_4(CLK_VDO1_26M_SLOW, "vdo1_26m_slow_ck", "clk26m", 8),
|
||||
/* VDO1_5 */
|
||||
GATE_VDO1_5(CLK_VDO1_DPI1_HDMI, "vdo1_dpi1_hdmi", "hdmi_txpll", 0),
|
||||
};
|
||||
|
||||
static const struct mtk_clk_desc vdo1_desc = {
|
||||
|
||||
@ -87,8 +87,8 @@ static int pxa1908_apmu_probe(struct platform_device *pdev)
|
||||
struct pxa1908_clk_unit *pxa_unit;
|
||||
|
||||
pxa_unit = devm_kzalloc(&pdev->dev, sizeof(*pxa_unit), GFP_KERNEL);
|
||||
if (IS_ERR(pxa_unit))
|
||||
return PTR_ERR(pxa_unit);
|
||||
if (!pxa_unit)
|
||||
return -ENOMEM;
|
||||
|
||||
pxa_unit->base = devm_platform_ioremap_resource(pdev, 0);
|
||||
if (IS_ERR(pxa_unit->base))
|
||||
|
||||
@ -170,11 +170,12 @@ static struct clk * __init rza2_cpg_clk_register(struct device *dev,
|
||||
if (IS_ERR(parent))
|
||||
return ERR_CAST(parent);
|
||||
|
||||
switch (core->id) {
|
||||
case CLK_MAIN:
|
||||
switch (core->type) {
|
||||
case CLK_TYPE_RZA_MAIN:
|
||||
r7s9210_update_clk_table(parent, base);
|
||||
break;
|
||||
|
||||
case CLK_PLL:
|
||||
case CLK_TYPE_RZA_PLL:
|
||||
if (cpg_mode)
|
||||
mult = 44; /* Divider 1 is 1/2 */
|
||||
else
|
||||
@ -185,9 +186,6 @@ static struct clk * __init rza2_cpg_clk_register(struct device *dev,
|
||||
return ERR_PTR(-EINVAL);
|
||||
}
|
||||
|
||||
if (core->id == CLK_MAIN)
|
||||
r7s9210_update_clk_table(parent, base);
|
||||
|
||||
return clk_register_fixed_factor(NULL, core->name,
|
||||
__clk_get_name(parent), 0, mult, div);
|
||||
}
|
||||
|
||||
@ -138,6 +138,10 @@ static const struct cpg_core_clk r8a779a0_core_clks[] __initconst = {
|
||||
};
|
||||
|
||||
static const struct mssr_mod_clk r8a779a0_mod_clks[] __initconst = {
|
||||
DEF_MOD("isp0", 16, R8A779A0_CLK_S1D1),
|
||||
DEF_MOD("isp1", 17, R8A779A0_CLK_S1D1),
|
||||
DEF_MOD("isp2", 18, R8A779A0_CLK_S1D1),
|
||||
DEF_MOD("isp3", 19, R8A779A0_CLK_S1D1),
|
||||
DEF_MOD("avb0", 211, R8A779A0_CLK_S3D2),
|
||||
DEF_MOD("avb1", 212, R8A779A0_CLK_S3D2),
|
||||
DEF_MOD("avb2", 213, R8A779A0_CLK_S3D2),
|
||||
@ -238,6 +242,10 @@ static const struct mssr_mod_clk r8a779a0_mod_clks[] __initconst = {
|
||||
DEF_MOD("vspx1", 1029, R8A779A0_CLK_S1D1),
|
||||
DEF_MOD("vspx2", 1030, R8A779A0_CLK_S1D1),
|
||||
DEF_MOD("vspx3", 1031, R8A779A0_CLK_S1D1),
|
||||
DEF_MOD("fcpvx0", 1100, R8A779A0_CLK_S1D1),
|
||||
DEF_MOD("fcpvx1", 1101, R8A779A0_CLK_S1D1),
|
||||
DEF_MOD("fcpvx2", 1102, R8A779A0_CLK_S1D1),
|
||||
DEF_MOD("fcpvx3", 1103, R8A779A0_CLK_S1D1),
|
||||
};
|
||||
|
||||
static const unsigned int r8a779a0_crit_mod_clks[] __initconst = {
|
||||
|
||||
@ -163,6 +163,8 @@ static const struct cpg_core_clk r8a779g0_core_clks[] __initconst = {
|
||||
};
|
||||
|
||||
static const struct mssr_mod_clk r8a779g0_mod_clks[] __initconst = {
|
||||
DEF_MOD("isp0", 16, R8A779G0_CLK_S0D2_VIO),
|
||||
DEF_MOD("isp1", 17, R8A779G0_CLK_S0D2_VIO),
|
||||
DEF_MOD("avb0", 211, R8A779G0_CLK_S0D4_HSC),
|
||||
DEF_MOD("avb1", 212, R8A779G0_CLK_S0D4_HSC),
|
||||
DEF_MOD("avb2", 213, R8A779G0_CLK_S0D4_HSC),
|
||||
|
||||
@ -171,6 +171,7 @@ static const struct cpg_core_clk r8a779h0_core_clks[] __initconst = {
|
||||
};
|
||||
|
||||
static const struct mssr_mod_clk r8a779h0_mod_clks[] __initconst = {
|
||||
DEF_MOD("isp0", 16, R8A779H0_CLK_S0D2_VIO),
|
||||
DEF_MOD("avb0:rgmii0", 211, R8A779H0_CLK_S0D8_HSC),
|
||||
DEF_MOD("avb1:rgmii1", 212, R8A779H0_CLK_S0D8_HSC),
|
||||
DEF_MOD("avb2:rgmii2", 213, R8A779H0_CLK_S0D8_HSC),
|
||||
@ -238,6 +239,8 @@ static const struct mssr_mod_clk r8a779h0_mod_clks[] __initconst = {
|
||||
DEF_MOD("pfc1", 916, R8A779H0_CLK_CP),
|
||||
DEF_MOD("pfc2", 917, R8A779H0_CLK_CP),
|
||||
DEF_MOD("tsc2:tsc1", 919, R8A779H0_CLK_CL16M),
|
||||
DEF_MOD("vspx0", 1028, R8A779H0_CLK_S0D1_VIO),
|
||||
DEF_MOD("fcpvx0", 1100, R8A779H0_CLK_S0D1_VIO),
|
||||
DEF_MOD("ssiu", 2926, R8A779H0_CLK_S0D6_PER),
|
||||
DEF_MOD("ssi", 2927, R8A779H0_CLK_S0D6_PER),
|
||||
};
|
||||
|
||||
@ -89,7 +89,9 @@ static const struct clk_div_table dtable_1_32[] = {
|
||||
|
||||
/* Mux clock tables */
|
||||
static const char * const sel_pll3_3[] = { ".pll3_533", ".pll3_400" };
|
||||
#ifdef CONFIG_ARM64
|
||||
static const char * const sel_pll6_2[] = { ".pll6_250", ".pll5_250" };
|
||||
#endif
|
||||
static const char * const sel_sdhi[] = { ".clk_533", ".clk_400", ".clk_266" };
|
||||
|
||||
static const u32 mtable_sdhi[] = { 1, 2, 3 };
|
||||
@ -137,7 +139,12 @@ static const struct cpg_core_clk r9a07g043_core_clks[] __initconst = {
|
||||
DEF_DIV("P2", R9A07G043_CLK_P2, CLK_PLL3_DIV2_4_2, DIVPL3A, dtable_1_32),
|
||||
DEF_FIXED("M0", R9A07G043_CLK_M0, CLK_PLL3_DIV2_4, 1, 1),
|
||||
DEF_FIXED("ZT", R9A07G043_CLK_ZT, CLK_PLL3_DIV2_4_2, 1, 1),
|
||||
#ifdef CONFIG_ARM64
|
||||
DEF_MUX("HP", R9A07G043_CLK_HP, SEL_PLL6_2, sel_pll6_2),
|
||||
#endif
|
||||
#ifdef CONFIG_RISCV
|
||||
DEF_FIXED("HP", R9A07G043_CLK_HP, CLK_PLL6_250, 1, 1),
|
||||
#endif
|
||||
DEF_FIXED("SPI0", R9A07G043_CLK_SPI0, CLK_DIV_PLL3_C, 1, 2),
|
||||
DEF_FIXED("SPI1", R9A07G043_CLK_SPI1, CLK_DIV_PLL3_C, 1, 4),
|
||||
DEF_SD_MUX("SD0", R9A07G043_CLK_SD0, SEL_SDHI0, SEL_SDHI0_STS, sel_sdhi,
|
||||
|
||||
@ -94,6 +94,41 @@ static const struct clk_div_table dtable_1_32[] = {
|
||||
{0, 0},
|
||||
};
|
||||
|
||||
#ifdef CONFIG_CLK_R9A07G054
|
||||
static const struct clk_div_table dtable_4_32[] = {
|
||||
{3, 4},
|
||||
{4, 5},
|
||||
{5, 6},
|
||||
{6, 7},
|
||||
{7, 8},
|
||||
{8, 9},
|
||||
{9, 10},
|
||||
{10, 11},
|
||||
{11, 12},
|
||||
{12, 13},
|
||||
{13, 14},
|
||||
{14, 15},
|
||||
{15, 16},
|
||||
{16, 17},
|
||||
{17, 18},
|
||||
{18, 19},
|
||||
{19, 20},
|
||||
{20, 21},
|
||||
{21, 22},
|
||||
{22, 23},
|
||||
{23, 24},
|
||||
{24, 25},
|
||||
{25, 26},
|
||||
{26, 27},
|
||||
{27, 28},
|
||||
{28, 29},
|
||||
{29, 30},
|
||||
{30, 31},
|
||||
{31, 32},
|
||||
{0, 0},
|
||||
};
|
||||
#endif
|
||||
|
||||
static const struct clk_div_table dtable_16_128[] = {
|
||||
{0, 16},
|
||||
{1, 32},
|
||||
@ -114,7 +149,7 @@ static const u32 mtable_sdhi[] = { 1, 2, 3 };
|
||||
static const struct {
|
||||
struct cpg_core_clk common[56];
|
||||
#ifdef CONFIG_CLK_R9A07G054
|
||||
struct cpg_core_clk drp[0];
|
||||
struct cpg_core_clk drp[3];
|
||||
#endif
|
||||
} core_clks __initconst = {
|
||||
.common = {
|
||||
@ -192,6 +227,9 @@ static const struct {
|
||||
},
|
||||
#ifdef CONFIG_CLK_R9A07G054
|
||||
.drp = {
|
||||
DEF_FIXED("DRP_M", R9A07G054_CLK_DRP_M, CLK_PLL3, 1, 5),
|
||||
DEF_FIXED("DRP_D", R9A07G054_CLK_DRP_D, CLK_PLL3, 1, 2),
|
||||
DEF_DIV("DRP_A", R9A07G054_CLK_DRP_A, CLK_PLL3, DIVPL3E, dtable_4_32),
|
||||
},
|
||||
#endif
|
||||
};
|
||||
@ -199,7 +237,7 @@ static const struct {
|
||||
static const struct {
|
||||
struct rzg2l_mod_clk common[79];
|
||||
#ifdef CONFIG_CLK_R9A07G054
|
||||
struct rzg2l_mod_clk drp[0];
|
||||
struct rzg2l_mod_clk drp[5];
|
||||
#endif
|
||||
} mod_clks = {
|
||||
.common = {
|
||||
@ -364,6 +402,16 @@ static const struct {
|
||||
},
|
||||
#ifdef CONFIG_CLK_R9A07G054
|
||||
.drp = {
|
||||
DEF_MOD("stpai_initclk", R9A07G054_STPAI_INITCLK, R9A07G044_OSCCLK,
|
||||
0x5e8, 0),
|
||||
DEF_MOD("stpai_aclk", R9A07G054_STPAI_ACLK, R9A07G044_CLK_P1,
|
||||
0x5e8, 1),
|
||||
DEF_MOD("stpai_mclk", R9A07G054_STPAI_MCLK, R9A07G054_CLK_DRP_M,
|
||||
0x5e8, 2),
|
||||
DEF_MOD("stpai_dclkin", R9A07G054_STPAI_DCLKIN, R9A07G054_CLK_DRP_D,
|
||||
0x5e8, 3),
|
||||
DEF_MOD("stpai_aclk_drp", R9A07G054_STPAI_ACLK_DRP, R9A07G054_CLK_DRP_A,
|
||||
0x5e8, 4),
|
||||
},
|
||||
#endif
|
||||
};
|
||||
@ -430,6 +478,9 @@ static const struct rzg2l_reset r9a07g044_resets[] = {
|
||||
DEF_RST(R9A07G044_ADC_PRESETN, 0x8a8, 0),
|
||||
DEF_RST(R9A07G044_ADC_ADRST_N, 0x8a8, 1),
|
||||
DEF_RST(R9A07G044_TSU_PRESETN, 0x8ac, 0),
|
||||
#ifdef CONFIG_CLK_R9A07G054
|
||||
DEF_RST(R9A07G054_STPAI_ARESETN, 0x8e8, 0),
|
||||
#endif
|
||||
};
|
||||
|
||||
static const unsigned int r9a07g044_crit_mod_clks[] __initconst = {
|
||||
|
||||
@ -51,7 +51,7 @@
|
||||
#define G3S_SEL_SDHI2 SEL_PLL_PACK(G3S_CPG_SDHI_DSEL, 8, 2)
|
||||
|
||||
/* PLL 1/4/6 configuration registers macro. */
|
||||
#define G3S_PLL146_CONF(clk1, clk2) ((clk1) << 22 | (clk2) << 12)
|
||||
#define G3S_PLL146_CONF(clk1, clk2, setting) ((clk1) << 22 | (clk2) << 12 | (setting))
|
||||
|
||||
#define DEF_G3S_MUX(_name, _id, _conf, _parent_names, _mux_flags, _clk_flags) \
|
||||
DEF_TYPE(_name, _id, CLK_TYPE_MUX, .conf = (_conf), \
|
||||
@ -134,7 +134,8 @@ static const struct cpg_core_clk r9a08g045_core_clks[] __initconst = {
|
||||
|
||||
/* Internal Core Clocks */
|
||||
DEF_FIXED(".osc_div1000", CLK_OSC_DIV1000, CLK_EXTAL, 1, 1000),
|
||||
DEF_G3S_PLL(".pll1", CLK_PLL1, CLK_EXTAL, G3S_PLL146_CONF(0x4, 0x8)),
|
||||
DEF_G3S_PLL(".pll1", CLK_PLL1, CLK_EXTAL, G3S_PLL146_CONF(0x4, 0x8, 0x100),
|
||||
1100000000UL),
|
||||
DEF_FIXED(".pll2", CLK_PLL2, CLK_EXTAL, 200, 3),
|
||||
DEF_FIXED(".pll3", CLK_PLL3, CLK_EXTAL, 200, 3),
|
||||
DEF_FIXED(".pll4", CLK_PLL4, CLK_EXTAL, 100, 3),
|
||||
@ -241,6 +242,7 @@ static const struct rzg2l_mod_clk r9a08g045_mod_clks[] = {
|
||||
DEF_MOD("gpio_hclk", R9A08G045_GPIO_HCLK, R9A08G045_OSCCLK, 0x598, 0),
|
||||
DEF_MOD("adc_adclk", R9A08G045_ADC_ADCLK, R9A08G045_CLK_TSU, 0x5a8, 0),
|
||||
DEF_MOD("adc_pclk", R9A08G045_ADC_PCLK, R9A08G045_CLK_TSU, 0x5a8, 1),
|
||||
DEF_MOD("tsu_pclk", R9A08G045_TSU_PCLK, R9A08G045_CLK_TSU, 0x5ac, 0),
|
||||
DEF_MOD("vbat_bclk", R9A08G045_VBAT_BCLK, R9A08G045_OSCCLK, 0x614, 0),
|
||||
};
|
||||
|
||||
@ -279,6 +281,7 @@ static const struct rzg2l_reset r9a08g045_resets[] = {
|
||||
DEF_RST(R9A08G045_GPIO_SPARE_RESETN, 0x898, 2),
|
||||
DEF_RST(R9A08G045_ADC_PRESETN, 0x8a8, 0),
|
||||
DEF_RST(R9A08G045_ADC_ADRST_N, 0x8a8, 1),
|
||||
DEF_RST(R9A08G045_TSU_PRESETN, 0x8ac, 0),
|
||||
DEF_RST(R9A08G045_VBAT_BRESETN, 0x914, 0),
|
||||
};
|
||||
|
||||
@ -353,6 +356,8 @@ static const struct rzg2l_cpg_pm_domain_init_data r9a08g045_pm_domains[] = {
|
||||
DEF_REG_CONF(CPG_BUS_MCPU3_MSTOP, BIT(4)), 0),
|
||||
DEF_PD("adc", R9A08G045_PD_ADC,
|
||||
DEF_REG_CONF(CPG_BUS_MCPU2_MSTOP, BIT(14)), 0),
|
||||
DEF_PD("tsu", R9A08G045_PD_TSU,
|
||||
DEF_REG_CONF(CPG_BUS_MCPU2_MSTOP, BIT(15)), 0),
|
||||
DEF_PD("vbat", R9A08G045_PD_VBAT,
|
||||
DEF_REG_CONF(CPG_BUS_MCPU3_MSTOP, BIT(8)),
|
||||
GENPD_FLAG_ALWAYS_ON),
|
||||
|
||||
@ -28,12 +28,19 @@ enum clk_ids {
|
||||
CLK_PLLCLN,
|
||||
CLK_PLLDTY,
|
||||
CLK_PLLCA55,
|
||||
CLK_PLLVDO,
|
||||
|
||||
/* Internal Core Clocks */
|
||||
CLK_PLLCM33_DIV16,
|
||||
CLK_PLLCLN_DIV2,
|
||||
CLK_PLLCLN_DIV8,
|
||||
CLK_PLLCLN_DIV16,
|
||||
CLK_PLLCLN_DIV20,
|
||||
CLK_PLLDTY_ACPU,
|
||||
CLK_PLLDTY_ACPU_DIV2,
|
||||
CLK_PLLDTY_ACPU_DIV4,
|
||||
CLK_PLLDTY_DIV16,
|
||||
CLK_PLLVDO_CRU0,
|
||||
|
||||
/* Module Clocks */
|
||||
MOD_CLK_BASE,
|
||||
@ -47,6 +54,12 @@ static const struct clk_div_table dtable_1_8[] = {
|
||||
{0, 0},
|
||||
};
|
||||
|
||||
static const struct clk_div_table dtable_2_4[] = {
|
||||
{0, 2},
|
||||
{1, 4},
|
||||
{0, 0},
|
||||
};
|
||||
|
||||
static const struct clk_div_table dtable_2_64[] = {
|
||||
{0, 2},
|
||||
{1, 4},
|
||||
@ -67,14 +80,22 @@ static const struct cpg_core_clk r9a09g047_core_clks[] __initconst = {
|
||||
DEF_FIXED(".pllcln", CLK_PLLCLN, CLK_QEXTAL, 200, 3),
|
||||
DEF_FIXED(".plldty", CLK_PLLDTY, CLK_QEXTAL, 200, 3),
|
||||
DEF_PLL(".pllca55", CLK_PLLCA55, CLK_QEXTAL, PLL_CONF(0x64)),
|
||||
DEF_FIXED(".pllvdo", CLK_PLLVDO, CLK_QEXTAL, 105, 2),
|
||||
|
||||
/* Internal Core Clocks */
|
||||
DEF_FIXED(".pllcm33_div16", CLK_PLLCM33_DIV16, CLK_PLLCM33, 1, 16),
|
||||
|
||||
DEF_FIXED(".pllcln_div2", CLK_PLLCLN_DIV2, CLK_PLLCLN, 1, 2),
|
||||
DEF_FIXED(".pllcln_div8", CLK_PLLCLN_DIV8, CLK_PLLCLN, 1, 8),
|
||||
DEF_FIXED(".pllcln_div16", CLK_PLLCLN_DIV16, CLK_PLLCLN, 1, 16),
|
||||
DEF_FIXED(".pllcln_div20", CLK_PLLCLN_DIV20, CLK_PLLCLN, 1, 20),
|
||||
|
||||
DEF_DDIV(".plldty_acpu", CLK_PLLDTY_ACPU, CLK_PLLDTY, CDDIV0_DIVCTL2, dtable_2_64),
|
||||
DEF_FIXED(".plldty_acpu_div2", CLK_PLLDTY_ACPU_DIV2, CLK_PLLDTY_ACPU, 1, 2),
|
||||
DEF_FIXED(".plldty_acpu_div4", CLK_PLLDTY_ACPU_DIV4, CLK_PLLDTY_ACPU, 1, 4),
|
||||
DEF_FIXED(".plldty_div16", CLK_PLLDTY_DIV16, CLK_PLLDTY, 1, 16),
|
||||
|
||||
DEF_DDIV(".pllvdo_cru0", CLK_PLLVDO_CRU0, CLK_PLLVDO, CDDIV3_DIVCTL3, dtable_2_4),
|
||||
|
||||
/* Core Clocks */
|
||||
DEF_FIXED("sys_0_pclk", R9A09G047_SYS_0_PCLK, CLK_QEXTAL, 1, 1),
|
||||
@ -90,8 +111,22 @@ static const struct cpg_core_clk r9a09g047_core_clks[] __initconst = {
|
||||
};
|
||||
|
||||
static const struct rzv2h_mod_clk r9a09g047_mod_clks[] __initconst = {
|
||||
DEF_MOD_CRITICAL("icu_0_pclk_i", CLK_PLLCM33_DIV16, 0, 5, 0, 5,
|
||||
BUS_MSTOP_NONE),
|
||||
DEF_MOD_CRITICAL("gic_0_gicclk", CLK_PLLDTY_ACPU_DIV4, 1, 3, 0, 19,
|
||||
BUS_MSTOP(3, BIT(5))),
|
||||
DEF_MOD("wdt_1_clkp", CLK_PLLCLN_DIV16, 4, 13, 2, 13,
|
||||
BUS_MSTOP(1, BIT(0))),
|
||||
DEF_MOD("wdt_1_clk_loco", CLK_QEXTAL, 4, 14, 2, 14,
|
||||
BUS_MSTOP(1, BIT(0))),
|
||||
DEF_MOD("wdt_2_clkp", CLK_PLLCLN_DIV16, 4, 15, 2, 15,
|
||||
BUS_MSTOP(5, BIT(12))),
|
||||
DEF_MOD("wdt_2_clk_loco", CLK_QEXTAL, 5, 0, 2, 16,
|
||||
BUS_MSTOP(5, BIT(12))),
|
||||
DEF_MOD("wdt_3_clkp", CLK_PLLCLN_DIV16, 5, 1, 2, 17,
|
||||
BUS_MSTOP(5, BIT(13))),
|
||||
DEF_MOD("wdt_3_clk_loco", CLK_QEXTAL, 5, 2, 2, 18,
|
||||
BUS_MSTOP(5, BIT(13))),
|
||||
DEF_MOD("scif_0_clk_pck", CLK_PLLCM33_DIV16, 8, 15, 4, 15,
|
||||
BUS_MSTOP(3, BIT(14))),
|
||||
DEF_MOD("riic_8_ckm", CLK_PLLCM33_DIV16, 9, 3, 4, 19,
|
||||
@ -112,12 +147,54 @@ static const struct rzv2h_mod_clk r9a09g047_mod_clks[] __initconst = {
|
||||
BUS_MSTOP(1, BIT(7))),
|
||||
DEF_MOD("riic_7_ckm", CLK_PLLCLN_DIV16, 9, 11, 4, 27,
|
||||
BUS_MSTOP(1, BIT(8))),
|
||||
DEF_MOD("canfd_0_pclk", CLK_PLLCLN_DIV16, 9, 12, 4, 28,
|
||||
BUS_MSTOP(10, BIT(14))),
|
||||
DEF_MOD("canfd_0_clk_ram", CLK_PLLCLN_DIV8, 9, 13, 4, 29,
|
||||
BUS_MSTOP(10, BIT(14))),
|
||||
DEF_MOD("canfd_0_clkc", CLK_PLLCLN_DIV20, 9, 14, 4, 30,
|
||||
BUS_MSTOP(10, BIT(14))),
|
||||
DEF_MOD("sdhi_0_imclk", CLK_PLLCLN_DIV8, 10, 3, 5, 3,
|
||||
BUS_MSTOP(8, BIT(2))),
|
||||
DEF_MOD("sdhi_0_imclk2", CLK_PLLCLN_DIV8, 10, 4, 5, 4,
|
||||
BUS_MSTOP(8, BIT(2))),
|
||||
DEF_MOD("sdhi_0_clk_hs", CLK_PLLCLN_DIV2, 10, 5, 5, 5,
|
||||
BUS_MSTOP(8, BIT(2))),
|
||||
DEF_MOD("sdhi_0_aclk", CLK_PLLDTY_ACPU_DIV4, 10, 6, 5, 6,
|
||||
BUS_MSTOP(8, BIT(2))),
|
||||
DEF_MOD("sdhi_1_imclk", CLK_PLLCLN_DIV8, 10, 7, 5, 7,
|
||||
BUS_MSTOP(8, BIT(3))),
|
||||
DEF_MOD("sdhi_1_imclk2", CLK_PLLCLN_DIV8, 10, 8, 5, 8,
|
||||
BUS_MSTOP(8, BIT(3))),
|
||||
DEF_MOD("sdhi_1_clk_hs", CLK_PLLCLN_DIV2, 10, 9, 5, 9,
|
||||
BUS_MSTOP(8, BIT(3))),
|
||||
DEF_MOD("sdhi_1_aclk", CLK_PLLDTY_ACPU_DIV4, 10, 10, 5, 10,
|
||||
BUS_MSTOP(8, BIT(3))),
|
||||
DEF_MOD("sdhi_2_imclk", CLK_PLLCLN_DIV8, 10, 11, 5, 11,
|
||||
BUS_MSTOP(8, BIT(4))),
|
||||
DEF_MOD("sdhi_2_imclk2", CLK_PLLCLN_DIV8, 10, 12, 5, 12,
|
||||
BUS_MSTOP(8, BIT(4))),
|
||||
DEF_MOD("sdhi_2_clk_hs", CLK_PLLCLN_DIV2, 10, 13, 5, 13,
|
||||
BUS_MSTOP(8, BIT(4))),
|
||||
DEF_MOD("sdhi_2_aclk", CLK_PLLDTY_ACPU_DIV4, 10, 14, 5, 14,
|
||||
BUS_MSTOP(8, BIT(4))),
|
||||
DEF_MOD("cru_0_aclk", CLK_PLLDTY_ACPU_DIV2, 13, 2, 6, 18,
|
||||
BUS_MSTOP(9, BIT(4))),
|
||||
DEF_MOD_NO_PM("cru_0_vclk", CLK_PLLVDO_CRU0, 13, 3, 6, 19,
|
||||
BUS_MSTOP(9, BIT(4))),
|
||||
DEF_MOD("cru_0_pclk", CLK_PLLDTY_DIV16, 13, 4, 6, 20,
|
||||
BUS_MSTOP(9, BIT(4))),
|
||||
DEF_MOD("tsu_1_pclk", CLK_QEXTAL, 16, 10, 8, 10,
|
||||
BUS_MSTOP(2, BIT(15))),
|
||||
};
|
||||
|
||||
static const struct rzv2h_reset r9a09g047_resets[] __initconst = {
|
||||
DEF_RST(3, 0, 1, 1), /* SYS_0_PRESETN */
|
||||
DEF_RST(3, 6, 1, 7), /* ICU_0_PRESETN_I */
|
||||
DEF_RST(3, 8, 1, 9), /* GIC_0_GICRESET_N */
|
||||
DEF_RST(3, 9, 1, 10), /* GIC_0_DBG_GICRESET_N */
|
||||
DEF_RST(7, 6, 3, 7), /* WDT_1_RESET */
|
||||
DEF_RST(7, 7, 3, 8), /* WDT_2_RESET */
|
||||
DEF_RST(7, 8, 3, 9), /* WDT_3_RESET */
|
||||
DEF_RST(9, 5, 4, 6), /* SCIF_0_RST_SYSTEM_N */
|
||||
DEF_RST(9, 8, 4, 9), /* RIIC_0_MRST */
|
||||
DEF_RST(9, 9, 4, 10), /* RIIC_1_MRST */
|
||||
@ -128,6 +205,15 @@ static const struct rzv2h_reset r9a09g047_resets[] __initconst = {
|
||||
DEF_RST(9, 14, 4, 15), /* RIIC_6_MRST */
|
||||
DEF_RST(9, 15, 4, 16), /* RIIC_7_MRST */
|
||||
DEF_RST(10, 0, 4, 17), /* RIIC_8_MRST */
|
||||
DEF_RST(10, 1, 4, 18), /* CANFD_0_RSTP_N */
|
||||
DEF_RST(10, 2, 4, 19), /* CANFD_0_RSTC_N */
|
||||
DEF_RST(10, 7, 4, 24), /* SDHI_0_IXRST */
|
||||
DEF_RST(10, 8, 4, 25), /* SDHI_1_IXRST */
|
||||
DEF_RST(10, 9, 4, 26), /* SDHI_2_IXRST */
|
||||
DEF_RST(12, 5, 5, 22), /* CRU_0_PRESETN */
|
||||
DEF_RST(12, 6, 5, 23), /* CRU_0_ARESETN */
|
||||
DEF_RST(12, 7, 5, 24), /* CRU_0_S_RESETN */
|
||||
DEF_RST(15, 8, 7, 9), /* TSU_1_PRESETN */
|
||||
};
|
||||
|
||||
const struct rzv2h_cpg_info r9a09g047_cpg_info __initconst = {
|
||||
|
||||
@ -31,6 +31,8 @@ enum clk_ids {
|
||||
CLK_PLLVDO,
|
||||
|
||||
/* Internal Core Clocks */
|
||||
CLK_PLLCM33_DIV4,
|
||||
CLK_PLLCM33_DIV4_PLLCM33,
|
||||
CLK_PLLCM33_DIV16,
|
||||
CLK_PLLCLN_DIV2,
|
||||
CLK_PLLCLN_DIV8,
|
||||
@ -39,6 +41,8 @@ enum clk_ids {
|
||||
CLK_PLLDTY_ACPU_DIV2,
|
||||
CLK_PLLDTY_ACPU_DIV4,
|
||||
CLK_PLLDTY_DIV16,
|
||||
CLK_PLLDTY_RCPU,
|
||||
CLK_PLLDTY_RCPU_DIV4,
|
||||
CLK_PLLVDO_CRU0,
|
||||
CLK_PLLVDO_CRU1,
|
||||
CLK_PLLVDO_CRU2,
|
||||
@ -85,6 +89,9 @@ static const struct cpg_core_clk r9a09g057_core_clks[] __initconst = {
|
||||
DEF_FIXED(".pllvdo", CLK_PLLVDO, CLK_QEXTAL, 105, 2),
|
||||
|
||||
/* Internal Core Clocks */
|
||||
DEF_FIXED(".pllcm33_div4", CLK_PLLCM33_DIV4, CLK_PLLCM33, 1, 4),
|
||||
DEF_DDIV(".pllcm33_div4_pllcm33", CLK_PLLCM33_DIV4_PLLCM33,
|
||||
CLK_PLLCM33_DIV4, CDDIV0_DIVCTL1, dtable_2_64),
|
||||
DEF_FIXED(".pllcm33_div16", CLK_PLLCM33_DIV16, CLK_PLLCM33, 1, 16),
|
||||
|
||||
DEF_FIXED(".pllcln_div2", CLK_PLLCLN_DIV2, CLK_PLLCLN, 1, 2),
|
||||
@ -95,6 +102,8 @@ static const struct cpg_core_clk r9a09g057_core_clks[] __initconst = {
|
||||
DEF_FIXED(".plldty_acpu_div2", CLK_PLLDTY_ACPU_DIV2, CLK_PLLDTY_ACPU, 1, 2),
|
||||
DEF_FIXED(".plldty_acpu_div4", CLK_PLLDTY_ACPU_DIV4, CLK_PLLDTY_ACPU, 1, 4),
|
||||
DEF_FIXED(".plldty_div16", CLK_PLLDTY_DIV16, CLK_PLLDTY, 1, 16),
|
||||
DEF_DDIV(".plldty_rcpu", CLK_PLLDTY_RCPU, CLK_PLLDTY, CDDIV3_DIVCTL2, dtable_2_64),
|
||||
DEF_FIXED(".plldty_rcpu_div4", CLK_PLLDTY_RCPU_DIV4, CLK_PLLDTY_RCPU, 1, 4),
|
||||
|
||||
DEF_DDIV(".pllvdo_cru0", CLK_PLLVDO_CRU0, CLK_PLLVDO, CDDIV3_DIVCTL3, dtable_2_4),
|
||||
DEF_DDIV(".pllvdo_cru1", CLK_PLLVDO_CRU1, CLK_PLLVDO, CDDIV4_DIVCTL0, dtable_2_4),
|
||||
@ -115,6 +124,16 @@ static const struct cpg_core_clk r9a09g057_core_clks[] __initconst = {
|
||||
};
|
||||
|
||||
static const struct rzv2h_mod_clk r9a09g057_mod_clks[] __initconst = {
|
||||
DEF_MOD("dmac_0_aclk", CLK_PLLCM33_DIV4_PLLCM33, 0, 0, 0, 0,
|
||||
BUS_MSTOP(5, BIT(9))),
|
||||
DEF_MOD("dmac_1_aclk", CLK_PLLDTY_ACPU_DIV2, 0, 1, 0, 1,
|
||||
BUS_MSTOP(3, BIT(2))),
|
||||
DEF_MOD("dmac_2_aclk", CLK_PLLDTY_ACPU_DIV2, 0, 2, 0, 2,
|
||||
BUS_MSTOP(3, BIT(3))),
|
||||
DEF_MOD("dmac_3_aclk", CLK_PLLDTY_RCPU_DIV4, 0, 3, 0, 3,
|
||||
BUS_MSTOP(10, BIT(11))),
|
||||
DEF_MOD("dmac_4_aclk", CLK_PLLDTY_RCPU_DIV4, 0, 4, 0, 4,
|
||||
BUS_MSTOP(10, BIT(12))),
|
||||
DEF_MOD_CRITICAL("icu_0_pclk_i", CLK_PLLCM33_DIV16, 0, 5, 0, 5,
|
||||
BUS_MSTOP_NONE),
|
||||
DEF_MOD_CRITICAL("gic_0_gicclk", CLK_PLLDTY_ACPU_DIV4, 1, 3, 0, 19,
|
||||
@ -223,6 +242,11 @@ static const struct rzv2h_mod_clk r9a09g057_mod_clks[] __initconst = {
|
||||
|
||||
static const struct rzv2h_reset r9a09g057_resets[] __initconst = {
|
||||
DEF_RST(3, 0, 1, 1), /* SYS_0_PRESETN */
|
||||
DEF_RST(3, 1, 1, 2), /* DMAC_0_ARESETN */
|
||||
DEF_RST(3, 2, 1, 3), /* DMAC_1_ARESETN */
|
||||
DEF_RST(3, 3, 1, 4), /* DMAC_2_ARESETN */
|
||||
DEF_RST(3, 4, 1, 5), /* DMAC_3_ARESETN */
|
||||
DEF_RST(3, 5, 1, 6), /* DMAC_4_ARESETN */
|
||||
DEF_RST(3, 6, 1, 7), /* ICU_0_PRESETN_I */
|
||||
DEF_RST(3, 8, 1, 9), /* GIC_0_GICRESET_N */
|
||||
DEF_RST(3, 9, 1, 10), /* GIC_0_DBG_GICRESET_N */
|
||||
|
||||
@ -338,11 +338,6 @@ static void __init cpg_mssr_register_core_clk(const struct cpg_core_clk *core,
|
||||
WARN_DEBUG(id >= priv->num_core_clks);
|
||||
WARN_DEBUG(PTR_ERR(priv->clks[id]) != -ENOENT);
|
||||
|
||||
if (!core->name) {
|
||||
/* Skip NULLified clock */
|
||||
return;
|
||||
}
|
||||
|
||||
switch (core->type) {
|
||||
case CLK_TYPE_IN:
|
||||
clk = of_clk_get_by_name(priv->np, core->name);
|
||||
|
||||
@ -51,6 +51,7 @@
|
||||
#define RZG3S_DIV_M GENMASK(25, 22)
|
||||
#define RZG3S_DIV_NI GENMASK(21, 13)
|
||||
#define RZG3S_DIV_NF GENMASK(12, 1)
|
||||
#define RZG3S_SEL_PLL BIT(0)
|
||||
|
||||
#define CLK_ON_R(reg) (reg)
|
||||
#define CLK_MON_R(reg) (0x180 + (reg))
|
||||
@ -60,6 +61,7 @@
|
||||
#define GET_REG_OFFSET(val) ((val >> 20) & 0xfff)
|
||||
#define GET_REG_SAMPLL_CLK1(val) ((val >> 22) & 0xfff)
|
||||
#define GET_REG_SAMPLL_CLK2(val) ((val >> 12) & 0xfff)
|
||||
#define GET_REG_SAMPLL_SETTING(val) ((val) & 0xfff)
|
||||
|
||||
#define CPG_WEN_BIT BIT(16)
|
||||
|
||||
@ -943,6 +945,7 @@ rzg2l_cpg_sipll5_register(const struct cpg_core_clk *core,
|
||||
|
||||
struct pll_clk {
|
||||
struct clk_hw hw;
|
||||
unsigned long default_rate;
|
||||
unsigned int conf;
|
||||
unsigned int type;
|
||||
void __iomem *base;
|
||||
@ -980,12 +983,19 @@ static unsigned long rzg3s_cpg_pll_clk_recalc_rate(struct clk_hw *hw,
|
||||
{
|
||||
struct pll_clk *pll_clk = to_pll(hw);
|
||||
struct rzg2l_cpg_priv *priv = pll_clk->priv;
|
||||
u32 nir, nfr, mr, pr, val;
|
||||
u32 nir, nfr, mr, pr, val, setting;
|
||||
u64 rate;
|
||||
|
||||
if (pll_clk->type != CLK_TYPE_G3S_PLL)
|
||||
return parent_rate;
|
||||
|
||||
setting = GET_REG_SAMPLL_SETTING(pll_clk->conf);
|
||||
if (setting) {
|
||||
val = readl(priv->base + setting);
|
||||
if (val & RZG3S_SEL_PLL)
|
||||
return pll_clk->default_rate;
|
||||
}
|
||||
|
||||
val = readl(priv->base + GET_REG_SAMPLL_CLK1(pll_clk->conf));
|
||||
|
||||
pr = 1 << FIELD_GET(RZG3S_DIV_P, val);
|
||||
@ -1038,6 +1048,7 @@ rzg2l_cpg_pll_clk_register(const struct cpg_core_clk *core,
|
||||
pll_clk->base = priv->base;
|
||||
pll_clk->priv = priv;
|
||||
pll_clk->type = core->type;
|
||||
pll_clk->default_rate = core->default_rate;
|
||||
|
||||
ret = devm_clk_hw_register(dev, &pll_clk->hw);
|
||||
if (ret)
|
||||
@ -1105,11 +1116,6 @@ rzg2l_cpg_register_core_clk(const struct cpg_core_clk *core,
|
||||
WARN_DEBUG(id >= priv->num_core_clks);
|
||||
WARN_DEBUG(PTR_ERR(priv->clks[id]) != -ENOENT);
|
||||
|
||||
if (!core->name) {
|
||||
/* Skip NULLified clock */
|
||||
return;
|
||||
}
|
||||
|
||||
switch (core->type) {
|
||||
case CLK_TYPE_IN:
|
||||
clk = of_clk_get_by_name(priv->dev->of_node, core->name);
|
||||
@ -1228,8 +1234,8 @@ static int rzg2l_mod_clock_endisable(struct clk_hw *hw, bool enable)
|
||||
error = readl_poll_timeout_atomic(priv->base + CLK_MON_R(reg), value,
|
||||
value & bitmask, 0, 10);
|
||||
if (error)
|
||||
dev_err(dev, "Failed to enable CLK_ON %p\n",
|
||||
priv->base + CLK_ON_R(reg));
|
||||
dev_err(dev, "Failed to enable CLK_ON 0x%x/%pC\n",
|
||||
CLK_ON_R(reg), hw->clk);
|
||||
|
||||
return error;
|
||||
}
|
||||
@ -1344,11 +1350,6 @@ rzg2l_cpg_register_mod_clk(const struct rzg2l_mod_clk *mod,
|
||||
WARN_DEBUG(mod->parent >= priv->num_core_clks + priv->num_mod_clks);
|
||||
WARN_DEBUG(PTR_ERR(priv->clks[id]) != -ENOENT);
|
||||
|
||||
if (!mod->name) {
|
||||
/* Skip NULLified clock */
|
||||
return;
|
||||
}
|
||||
|
||||
parent = priv->clks[mod->parent];
|
||||
if (IS_ERR(parent)) {
|
||||
clk = parent;
|
||||
@ -1538,28 +1539,6 @@ static int rzg2l_cpg_reset_controller_register(struct rzg2l_cpg_priv *priv)
|
||||
return devm_reset_controller_register(priv->dev, &priv->rcdev);
|
||||
}
|
||||
|
||||
static bool rzg2l_cpg_is_pm_clk(struct rzg2l_cpg_priv *priv,
|
||||
const struct of_phandle_args *clkspec)
|
||||
{
|
||||
const struct rzg2l_cpg_info *info = priv->info;
|
||||
unsigned int id;
|
||||
unsigned int i;
|
||||
|
||||
if (clkspec->args_count != 2)
|
||||
return false;
|
||||
|
||||
if (clkspec->args[0] != CPG_MOD)
|
||||
return false;
|
||||
|
||||
id = clkspec->args[1] + info->num_total_core_clks;
|
||||
for (i = 0; i < info->num_no_pm_mod_clks; i++) {
|
||||
if (info->no_pm_mod_clks[i] == id)
|
||||
return false;
|
||||
}
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
/**
|
||||
* struct rzg2l_cpg_pm_domains - RZ/G2L PM domains data structure
|
||||
* @onecell_data: cell data
|
||||
@ -1584,45 +1563,73 @@ struct rzg2l_cpg_pd {
|
||||
u16 id;
|
||||
};
|
||||
|
||||
static bool rzg2l_cpg_is_pm_clk(struct rzg2l_cpg_pd *pd,
|
||||
const struct of_phandle_args *clkspec)
|
||||
{
|
||||
if (clkspec->np != pd->genpd.dev.of_node || clkspec->args_count != 2)
|
||||
return false;
|
||||
|
||||
switch (clkspec->args[0]) {
|
||||
case CPG_MOD: {
|
||||
struct rzg2l_cpg_priv *priv = pd->priv;
|
||||
const struct rzg2l_cpg_info *info = priv->info;
|
||||
unsigned int id = clkspec->args[1];
|
||||
|
||||
if (id >= priv->num_mod_clks)
|
||||
return false;
|
||||
|
||||
id += info->num_total_core_clks;
|
||||
|
||||
for (unsigned int i = 0; i < info->num_no_pm_mod_clks; i++) {
|
||||
if (info->no_pm_mod_clks[i] == id)
|
||||
return false;
|
||||
}
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
case CPG_CORE:
|
||||
default:
|
||||
return false;
|
||||
}
|
||||
}
|
||||
|
||||
static int rzg2l_cpg_attach_dev(struct generic_pm_domain *domain, struct device *dev)
|
||||
{
|
||||
struct rzg2l_cpg_pd *pd = container_of(domain, struct rzg2l_cpg_pd, genpd);
|
||||
struct rzg2l_cpg_priv *priv = pd->priv;
|
||||
struct device_node *np = dev->of_node;
|
||||
struct of_phandle_args clkspec;
|
||||
bool once = true;
|
||||
struct clk *clk;
|
||||
unsigned int i;
|
||||
int error;
|
||||
int i = 0;
|
||||
|
||||
while (!of_parse_phandle_with_args(np, "clocks", "#clock-cells", i,
|
||||
&clkspec)) {
|
||||
if (rzg2l_cpg_is_pm_clk(priv, &clkspec)) {
|
||||
if (once) {
|
||||
once = false;
|
||||
error = pm_clk_create(dev);
|
||||
if (error) {
|
||||
of_node_put(clkspec.np);
|
||||
goto err;
|
||||
}
|
||||
}
|
||||
clk = of_clk_get_from_provider(&clkspec);
|
||||
of_node_put(clkspec.np);
|
||||
if (IS_ERR(clk)) {
|
||||
error = PTR_ERR(clk);
|
||||
goto fail_destroy;
|
||||
}
|
||||
|
||||
error = pm_clk_add_clk(dev, clk);
|
||||
if (error) {
|
||||
dev_err(dev, "pm_clk_add_clk failed %d\n",
|
||||
error);
|
||||
goto fail_put;
|
||||
}
|
||||
} else {
|
||||
for (i = 0; !of_parse_phandle_with_args(np, "clocks", "#clock-cells", i, &clkspec); i++) {
|
||||
if (!rzg2l_cpg_is_pm_clk(pd, &clkspec)) {
|
||||
of_node_put(clkspec.np);
|
||||
continue;
|
||||
}
|
||||
|
||||
if (once) {
|
||||
once = false;
|
||||
error = pm_clk_create(dev);
|
||||
if (error) {
|
||||
of_node_put(clkspec.np);
|
||||
goto err;
|
||||
}
|
||||
}
|
||||
clk = of_clk_get_from_provider(&clkspec);
|
||||
of_node_put(clkspec.np);
|
||||
if (IS_ERR(clk)) {
|
||||
error = PTR_ERR(clk);
|
||||
goto fail_destroy;
|
||||
}
|
||||
|
||||
error = pm_clk_add_clk(dev, clk);
|
||||
if (error) {
|
||||
dev_err(dev, "pm_clk_add_clk failed %d\n", error);
|
||||
goto fail_put;
|
||||
}
|
||||
i++;
|
||||
}
|
||||
|
||||
return 0;
|
||||
|
||||
@ -21,6 +21,7 @@
|
||||
#define CPG_PL2_DDIV (0x204)
|
||||
#define CPG_PL3A_DDIV (0x208)
|
||||
#define CPG_PL6_DDIV (0x210)
|
||||
#define CPG_PL3C_SDIV (0x214)
|
||||
#define CPG_CLKSTATUS (0x280)
|
||||
#define CPG_PL3_SSEL (0x408)
|
||||
#define CPG_PL6_SSEL (0x414)
|
||||
@ -70,6 +71,7 @@
|
||||
#define DIVPL3A DDIV_PACK(CPG_PL3A_DDIV, 0, 3)
|
||||
#define DIVPL3B DDIV_PACK(CPG_PL3A_DDIV, 4, 3)
|
||||
#define DIVPL3C DDIV_PACK(CPG_PL3A_DDIV, 8, 3)
|
||||
#define DIVPL3E DDIV_PACK(CPG_PL3C_SDIV, 8, 5)
|
||||
#define DIVGPU DDIV_PACK(CPG_PL6_DDIV, 0, 2)
|
||||
|
||||
#define SEL_PLL_PACK(offset, bitpos, size) \
|
||||
@ -102,7 +104,10 @@ struct cpg_core_clk {
|
||||
const struct clk_div_table *dtable;
|
||||
const u32 *mtable;
|
||||
const unsigned long invalid_rate;
|
||||
const unsigned long max_rate;
|
||||
union {
|
||||
const unsigned long max_rate;
|
||||
const unsigned long default_rate;
|
||||
};
|
||||
const char * const *parent_names;
|
||||
notifier_fn_t notifier;
|
||||
u32 flag;
|
||||
@ -144,8 +149,9 @@ enum clk_types {
|
||||
DEF_TYPE(_name, _id, _type, .parent = _parent)
|
||||
#define DEF_SAMPLL(_name, _id, _parent, _conf) \
|
||||
DEF_TYPE(_name, _id, CLK_TYPE_SAM_PLL, .parent = _parent, .conf = _conf)
|
||||
#define DEF_G3S_PLL(_name, _id, _parent, _conf) \
|
||||
DEF_TYPE(_name, _id, CLK_TYPE_G3S_PLL, .parent = _parent, .conf = _conf)
|
||||
#define DEF_G3S_PLL(_name, _id, _parent, _conf, _default_rate) \
|
||||
DEF_TYPE(_name, _id, CLK_TYPE_G3S_PLL, .parent = _parent, .conf = _conf, \
|
||||
.default_rate = _default_rate)
|
||||
#define DEF_INPUT(_name, _id) \
|
||||
DEF_TYPE(_name, _id, CLK_TYPE_IN)
|
||||
#define DEF_FIXED(_name, _id, _parent, _mult, _div) \
|
||||
|
||||
@ -447,8 +447,7 @@ static void rzv2h_mod_clock_mstop_enable(struct rzv2h_cpg_priv *priv,
|
||||
{
|
||||
unsigned long mstop_mask = FIELD_GET(BUS_MSTOP_BITS_MASK, mstop_data);
|
||||
u16 mstop_index = FIELD_GET(BUS_MSTOP_IDX_MASK, mstop_data);
|
||||
unsigned int index = (mstop_index - 1) * 16;
|
||||
atomic_t *mstop = &priv->mstop_count[index];
|
||||
atomic_t *mstop = &priv->mstop_count[mstop_index * 16];
|
||||
unsigned long flags;
|
||||
unsigned int i;
|
||||
u32 val = 0;
|
||||
@ -469,8 +468,7 @@ static void rzv2h_mod_clock_mstop_disable(struct rzv2h_cpg_priv *priv,
|
||||
{
|
||||
unsigned long mstop_mask = FIELD_GET(BUS_MSTOP_BITS_MASK, mstop_data);
|
||||
u16 mstop_index = FIELD_GET(BUS_MSTOP_IDX_MASK, mstop_data);
|
||||
unsigned int index = (mstop_index - 1) * 16;
|
||||
atomic_t *mstop = &priv->mstop_count[index];
|
||||
atomic_t *mstop = &priv->mstop_count[mstop_index * 16];
|
||||
unsigned long flags;
|
||||
unsigned int i;
|
||||
u32 val = 0;
|
||||
@ -541,8 +539,8 @@ static int rzv2h_mod_clock_endisable(struct clk_hw *hw, bool enable)
|
||||
error = readl_poll_timeout_atomic(priv->base + reg, value,
|
||||
value & bitmask, 0, 10);
|
||||
if (error)
|
||||
dev_err(dev, "Failed to enable CLK_ON %p\n",
|
||||
priv->base + reg);
|
||||
dev_err(dev, "Failed to enable CLK_ON 0x%x/%pC\n",
|
||||
GET_CLK_ON_OFFSET(clock->on_index), hw->clk);
|
||||
|
||||
return error;
|
||||
}
|
||||
@ -630,8 +628,7 @@ rzv2h_cpg_register_mod_clk(const struct rzv2h_mod_clk *mod,
|
||||
} else if (clock->mstop_data != BUS_MSTOP_NONE && mod->critical) {
|
||||
unsigned long mstop_mask = FIELD_GET(BUS_MSTOP_BITS_MASK, clock->mstop_data);
|
||||
u16 mstop_index = FIELD_GET(BUS_MSTOP_IDX_MASK, clock->mstop_data);
|
||||
unsigned int index = (mstop_index - 1) * 16;
|
||||
atomic_t *mstop = &priv->mstop_count[index];
|
||||
atomic_t *mstop = &priv->mstop_count[mstop_index * 16];
|
||||
unsigned long flags;
|
||||
unsigned int i;
|
||||
u32 val = 0;
|
||||
@ -926,6 +923,9 @@ static int __init rzv2h_cpg_probe(struct platform_device *pdev)
|
||||
if (!priv->mstop_count)
|
||||
return -ENOMEM;
|
||||
|
||||
/* Adjust for CPG_BUS_m_MSTOP starting from m = 1 */
|
||||
priv->mstop_count -= 16;
|
||||
|
||||
priv->resets = devm_kmemdup(dev, info->resets, sizeof(*info->resets) *
|
||||
info->num_resets, GFP_KERNEL);
|
||||
if (!priv->resets)
|
||||
|
||||
@ -38,11 +38,13 @@ struct ddiv {
|
||||
#define CPG_CDDIV3 (0x40C)
|
||||
#define CPG_CDDIV4 (0x410)
|
||||
|
||||
#define CDDIV0_DIVCTL1 DDIV_PACK(CPG_CDDIV0, 4, 3, 1)
|
||||
#define CDDIV0_DIVCTL2 DDIV_PACK(CPG_CDDIV0, 8, 3, 2)
|
||||
#define CDDIV1_DIVCTL0 DDIV_PACK(CPG_CDDIV1, 0, 2, 4)
|
||||
#define CDDIV1_DIVCTL1 DDIV_PACK(CPG_CDDIV1, 4, 2, 5)
|
||||
#define CDDIV1_DIVCTL2 DDIV_PACK(CPG_CDDIV1, 8, 2, 6)
|
||||
#define CDDIV1_DIVCTL3 DDIV_PACK(CPG_CDDIV1, 12, 2, 7)
|
||||
#define CDDIV3_DIVCTL2 DDIV_PACK(CPG_CDDIV3, 8, 3, 14)
|
||||
#define CDDIV3_DIVCTL3 DDIV_PACK(CPG_CDDIV3, 12, 1, 15)
|
||||
#define CDDIV4_DIVCTL0 DDIV_PACK(CPG_CDDIV4, 0, 1, 16)
|
||||
#define CDDIV4_DIVCTL1 DDIV_PACK(CPG_CDDIV4, 4, 1, 17)
|
||||
|
||||
@ -721,6 +721,6 @@
|
||||
#define CLK_VDO1_DPINTF 58
|
||||
#define CLK_VDO1_DISP_MONITOR_DPINTF 59
|
||||
#define CLK_VDO1_26M_SLOW 60
|
||||
#define CLK_VDO1_NR_CLK 61
|
||||
#define CLK_VDO1_DPI1_HDMI 61
|
||||
|
||||
#endif /* _DT_BINDINGS_CLK_MT8188_H */
|
||||
|
||||
@ -12,12 +12,6 @@
|
||||
#include <linux/regmap.h>
|
||||
|
||||
/* function for registering clocks in early boot */
|
||||
|
||||
#ifdef CONFIG_ARCH_DAVINCI_DA830
|
||||
int da830_pll_init(struct device *dev, void __iomem *base, struct regmap *cfgchip);
|
||||
#endif
|
||||
#ifdef CONFIG_ARCH_DAVINCI_DA850
|
||||
int da850_pll0_init(struct device *dev, void __iomem *base, struct regmap *cfgchip);
|
||||
#endif
|
||||
|
||||
#endif /* __LINUX_CLK_DAVINCI_PLL_H___ */
|
||||
|
||||
Loading…
Reference in New Issue
Block a user