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spi: spi-fsl-lpspi: Clear status register after disabling the module
Clear the error flags after disabling the module to avoid the case when a flag is set again between flag clear and module disable. And use SR_CLEAR_MASK to replace hardcoded value for improved readability. Although fsl_lpspi_reset() was only introduced in commita15dc3d657
("spi: lpspi: Fix CLK pin becomes low before one transfer"), the original driver only reset SR in the interrupt handler, making it vulnerable to the same issue. Therefore the fixes commit is set at the introduction of the driver. Fixes:5314987de5
("spi: imx: add lpspi bus driver") Signed-off-by: Larisa Grigore <larisa.grigore@nxp.com> Signed-off-by: Ciprian Marian Costea <ciprianmarian.costea@nxp.com> Reviewed-by: Frank Li <Frank.Li@nxp.com> Signed-off-by: James Clark <james.clark@linaro.org> Link: https://patch.msgid.link/20250828-james-nxp-lpspi-v2-4-6262b9aa9be4@linaro.org Signed-off-by: Mark Brown <broonie@kernel.org>
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parent
e811b088a3
commit
dedf9c93de
@ -83,6 +83,8 @@
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#define TCR_RXMSK BIT(19)
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#define TCR_TXMSK BIT(18)
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#define SR_CLEAR_MASK GENMASK(13, 8)
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struct fsl_lpspi_devtype_data {
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u8 prescale_max;
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};
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@ -535,14 +537,13 @@ static int fsl_lpspi_reset(struct fsl_lpspi_data *fsl_lpspi)
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fsl_lpspi_intctrl(fsl_lpspi, 0);
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}
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/* W1C for all flags in SR */
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temp = 0x3F << 8;
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writel(temp, fsl_lpspi->base + IMX7ULP_SR);
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/* Clear FIFO and disable module */
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temp = CR_RRF | CR_RTF;
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writel(temp, fsl_lpspi->base + IMX7ULP_CR);
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/* W1C for all flags in SR */
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writel(SR_CLEAR_MASK, fsl_lpspi->base + IMX7ULP_SR);
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return 0;
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}
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