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76534860f1
From SAMA5D4, the watchdog timer is upgrated with a new feature, which is describled as in the datasheet, "WDT_MR can be written until a LOCKMR command is issued in WDT_CR". That is to say, as long as the bootstrap and u-boot don't issue a LOCKMR command, WDT_MR can be written more than once in the driver. So the SAMA5D4 watchdog driver's implementation is different from the at91sam9260 watchdog driver implemented in file at91sam9_wdt.c. The user application open the device file to enable the watchdog timer hardware, and close to disable it, and set the watchdog timer timeout by seting WDV and WDD fields of WDT_MR register, and ping the watchdog by issuing WDRSTT command to WDT_CR register with hard-coded key. Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com> Reviewed-by: Guenter Roeck <linux@roeck-us.net> Signed-off-by: Wim Van Sebroeck <wim@iguana.be>
40 lines
1.5 KiB
C
40 lines
1.5 KiB
C
/*
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* drivers/watchdog/at91sam9_wdt.h
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*
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* Copyright (C) 2007 Andrew Victor
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* Copyright (C) 2007 Atmel Corporation.
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*
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* Watchdog Timer (WDT) - System peripherals regsters.
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* Based on AT91SAM9261 datasheet revision D.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*/
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#ifndef AT91_WDT_H
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#define AT91_WDT_H
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#define AT91_WDT_CR 0x00 /* Watchdog Control Register */
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#define AT91_WDT_WDRSTT (1 << 0) /* Restart */
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#define AT91_WDT_KEY (0xa5 << 24) /* KEY Password */
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#define AT91_WDT_MR 0x04 /* Watchdog Mode Register */
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#define AT91_WDT_WDV (0xfff << 0) /* Counter Value */
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#define AT91_WDT_SET_WDV(x) ((x) & AT91_WDT_WDV)
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#define AT91_WDT_WDFIEN (1 << 12) /* Fault Interrupt Enable */
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#define AT91_WDT_WDRSTEN (1 << 13) /* Reset Processor */
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#define AT91_WDT_WDRPROC (1 << 14) /* Timer Restart */
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#define AT91_WDT_WDDIS (1 << 15) /* Watchdog Disable */
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#define AT91_WDT_WDD (0xfff << 16) /* Delta Value */
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#define AT91_WDT_SET_WDD(x) (((x) << 16) & AT91_WDT_WDD)
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#define AT91_WDT_WDDBGHLT (1 << 28) /* Debug Halt */
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#define AT91_WDT_WDIDLEHLT (1 << 29) /* Idle Halt */
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#define AT91_WDT_SR 0x08 /* Watchdog Status Register */
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#define AT91_WDT_WDUNF (1 << 0) /* Watchdog Underflow */
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#define AT91_WDT_WDERR (1 << 1) /* Watchdog Error */
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#endif
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