Stephen Boyd d10ebc7c64 Merge branches 'clk-bindings', 'clk-starfive', 'clk-rm', 'clk-renesas' and 'clk-cleanup' into clk-next ... - Remove OXNAS clk driver * clk-bindings: dt-bindings: clock: versal: Convert the xlnx,zynqmp-clk.txt to yaml dt-bindings: clock: xlnx,versal-clk: drop select:false dt-bindings: clock: versal: Add versal-net compatible string dt-bindings: clock: ast2600: Add I3C and MAC reset definitions dt-bindings: arm: hisilicon,cpuctrl: Merge "hisilicon,hix5hd2-clock" into parent binding * clk-starfive: reset: starfive: jh7110: Add StarFive STG/ISP/VOUT resets support clk: starfive: Simplify .determine_rate() clk: starfive: Add StarFive JH7110 Video-Output clock driver clk: starfive: Add StarFive JH7110 Image-Signal-Process clock driver clk: starfive: Add StarFive JH7110 System-Top-Group clock driver clk: starfive: jh7110-sys: Add PLL clocks source from DTS clk: starfive: Add StarFive JH7110 PLL clock driver dt-bindings: clock: Add StarFive JH7110 Video-Output clock and reset generator dt-bindings: clock: Add StarFive JH7110 Image-Signal-Process clock and reset generator dt-bindings: clock: Add StarFive JH7110 System-Top-Group clock and reset generator dt-bindings: clock: jh7110-syscrg: Add PLL clock inputs dt-bindings: soc: starfive: Add StarFive syscon module dt-bindings: clock: Add StarFive JH7110 PLL clock generator * clk-rm: dt-bindings: clk: oxnas: remove obsolete bindings clk: oxnas: remove obsolete clock driver * clk-renesas: clk: renesas: rcar-gen3: Add ADG clocks clk: renesas: r8a77965: Add 3DGE and ZG support clk: renesas: r8a7796: Add 3DGE and ZG support clk: renesas: r8a7795: Add 3DGE and ZG support clk: renesas: emev2: Remove obsolete clkdev registration clk: renesas: r9a07g043: Add MTU3a clock and reset entry clk: renesas: rzg2l: Simplify .determine_rate() clk: renesas: r9a09g011: Add CSI related clocks clk: renesas: r8a774b1: Add 3DGE and ZG support clk: renesas: r8a774e1: Add 3DGE and ZG support clk: renesas: r8a774a1: Add 3DGE and ZG support clk: renesas: rcar-gen3: Add support for ZG clock * clk-cleanup: clk: mvebu: Convert to devm_platform_ioremap_resource() clk: nuvoton: Convert to devm_platform_ioremap_resource() clk: socfpga: agilex: Convert to devm_platform_ioremap_resource() clk: ti: Use devm_platform_get_and_ioremap_resource() clk: mediatek: Convert to devm_platform_ioremap_resource() clk: hsdk-pll: Convert to devm_platform_ioremap_resource() clk: gemini: Convert to devm_platform_ioremap_resource() clk: fsl-sai: Convert to devm_platform_ioremap_resource() clk: bm1880: Convert to devm_platform_ioremap_resource() clk: axm5516: Convert to devm_platform_ioremap_resource() clk: actions: Convert to devm_platform_ioremap_resource() clk: cdce925: Remove redundant of_match_ptr() drivers: clk: keystone: Fix parameter judgment in _of_pll_clk_init() clk: Explicitly include correct DT includes		2023-08-30 14:37:45 -07:00
..
clk-div6.c
clk-div6.h
clk-emev2.c	clk: renesas: emev2: Remove obsolete clkdev registration	2023-07-27 14:32:41 +02:00
clk-mstp.c
clk-r8a73a4.c
clk-r8a7740.c
clk-r8a7778.c
clk-r8a7779.c
clk-rz.c
clk-sh73a0.c
Kconfig
Makefile
r7s9210-cpg-mssr.c
r8a774a1-cpg-mssr.c	clk: renesas: rcar-gen3: Add ADG clocks	2023-08-15 11:34:43 +02:00
r8a774b1-cpg-mssr.c	clk: renesas: rcar-gen3: Add ADG clocks	2023-08-15 11:34:43 +02:00
r8a774c0-cpg-mssr.c	clk: renesas: rcar-gen3: Add ADG clocks	2023-08-15 11:34:43 +02:00
r8a774e1-cpg-mssr.c	clk: renesas: rcar-gen3: Add ADG clocks	2023-08-15 11:34:43 +02:00
r8a779a0-cpg-mssr.c
r8a779f0-cpg-mssr.c
r8a779g0-cpg-mssr.c
r8a7742-cpg-mssr.c
r8a7743-cpg-mssr.c
r8a7745-cpg-mssr.c
r8a7790-cpg-mssr.c
r8a7791-cpg-mssr.c
r8a7792-cpg-mssr.c
r8a7794-cpg-mssr.c
r8a7795-cpg-mssr.c	clk: renesas: rcar-gen3: Add ADG clocks	2023-08-15 11:34:43 +02:00
r8a7796-cpg-mssr.c	clk: renesas: rcar-gen3: Add ADG clocks	2023-08-15 11:34:43 +02:00
r8a77470-cpg-mssr.c
r8a77965-cpg-mssr.c	clk: renesas: rcar-gen3: Add ADG clocks	2023-08-15 11:34:43 +02:00
r8a77970-cpg-mssr.c
r8a77980-cpg-mssr.c
r8a77990-cpg-mssr.c	clk: renesas: rcar-gen3: Add ADG clocks	2023-08-15 11:34:43 +02:00
r8a77995-cpg-mssr.c	clk: renesas: rcar-gen3: Add ADG clocks	2023-08-15 11:34:43 +02:00
r9a06g032-clocks.c
r9a07g043-cpg.c	clk: renesas: r9a07g043: Add MTU3a clock and reset entry	2023-07-25 11:12:28 +02:00
r9a07g044-cpg.c
r9a09g011-cpg.c	clk: renesas: r9a09g011: Add CSI related clocks	2023-07-10 09:31:53 +02:00
rcar-cpg-lib.c
rcar-cpg-lib.h
rcar-gen2-cpg.c
rcar-gen2-cpg.h
rcar-gen3-cpg.c
rcar-gen3-cpg.h
rcar-gen4-cpg.c
rcar-gen4-cpg.h
rcar-usb2-clock-sel.c	clk: Explicitly include correct DT includes	2023-07-19 13:13:16 -07:00
renesas-cpg-mssr.c	clk: Explicitly include correct DT includes	2023-07-19 13:13:16 -07:00
renesas-cpg-mssr.h
rzg2l-cpg.c	Merge branches 'clk-bindings', 'clk-starfive', 'clk-rm', 'clk-renesas' and 'clk-cleanup' into clk-next	2023-08-30 14:37:45 -07:00
rzg2l-cpg.h