Subbaraya Sundeep 691d30b0cd octeontx2: Set appropriate PF, VF masks and shifts based on silicon ... [ Upstream commit 25d51ebf0f ] Number of RVU PFs on CN20K silicon have increased to 96 from maximum of 32 that were supported on earlier silicons. Every RVU PF and VF is identified by HW using a 16bit PF_FUNC value. Due to the change in Max number of PFs in CN20K, the bit encoding of this PF_FUNC has changed. This patch handles the change by using helper functions(using silicon check) to use PF,VF masks and shifts to support both new silicon CN20K, OcteonTx series. These helper functions are used in different modules. Also moved the NIX AF register offset macros to other files which will be posted in coming patches. Signed-off-by: Subbaraya Sundeep <sbhatta@marvell.com> Signed-off-by: Sai Krishna <saikrishnag@marvell.com> Signed-off-by: Sunil Kovvuri Goutham <sgoutham@marvell.com> Link: https://patch.msgid.link/1749639716-13868-2-git-send-email-sbhatta@marvell.com Signed-off-by: Jakub Kicinski <kuba@kernel.org> Stable-dep-of: d280233fc8 ("Octeontx2-af: Fix NIX X2P calibration failures") Signed-off-by: Sasha Levin <sashal@kernel.org>		2025-09-04 16:55:37 +02:00
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marvell	octeontx2: Set appropriate PF, VF masks and shifts based on silicon	2025-09-04 16:55:37 +02:00
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