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https://kernel.googlesource.com/pub/scm/linux/kernel/git/stable/linux-stable.git
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4473949074
Apart from some slight naming and grouping differences, the new metrics
are functionally the same as the existing ones. Any missing metrics were
manually appended to the end of the auto generated file.
For the events, the new data includes descriptions that may have product
specific details and new groupings that will be consistent with other
products.
After generating the metrics from the telemetry repo [1], the following
manual steps were performed:
* Change the topdown expressions to compare on CPUID and use
#slots so that the same data can be shared between N2 and V2. Apart
from these modifications, the expressions now match more closely with
the Arm telemetry data which will hopefully make future updates
easier.
* Append some metrics from the old N2/V2 data that aren't present in
the telemetry data. These will possibly be added to the
telemetry-solution repo at a later time:
l3d_cache_mpki, l3d_cache_miss_rate, branch_pki, ipc_rate, spec_ipc,
retired_rate, wasted_rate, branch_immed_spec_rate,
branch_return_spec_rate, branch_indirect_spec_rate
[1]: https://gitlab.arm.com/telemetry-solution/telemetry-solution/-/blob/main/data/pmu/cpu/neoverse/neoverse-n2.json
Signed-off-by: James Clark <james.clark@arm.com>
Reviewed-by: John Garry <john.g.garry@oracle.com>
Cc: Adrian Hunter <adrian.hunter@intel.com>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Andrii Nakryiko <andrii@kernel.org>
Cc: Eduard Zingerman <eddyz87@gmail.com>
Cc: Haixin Yu <yuhaixin.yhx@linux.alibaba.com>
Cc: Ian Rogers <irogers@google.com>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Jing Zhang <renyu.zj@linux.alibaba.com>
Cc: Jiri Olsa <jolsa@kernel.org>
Cc: Kajol Jain <kjain@linux.ibm.com>
Cc: Kan Liang <kan.liang@linux.intel.com>
Cc: Leo Yan <leo.yan@linaro.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Mike Leach <mike.leach@linaro.org>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Nick Forrington <nick.forrington@arm.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Rob Herring <robh@kernel.org>
Cc: Sohom Datta <sohomdatta1@gmail.com>
Cc: Will Deacon <will@kernel.org>
Cc: linux-arm-kernel@lists.infradead.org
Link: https://lore.kernel.org/r/20230816114841.1679234-7-james.clark@arm.com
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
47 lines
3.8 KiB
JSON
47 lines
3.8 KiB
JSON
[
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{
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"ArchStdEvent": "MEM_ACCESS",
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"PublicDescription": "Counts memory accesses issued by the CPU load store unit, where those accesses are issued due to load or store operations. This event counts memory accesses no matter whether the data is received from any level of cache hierarchy or external memory. If memory accesses are broken up into smaller transactions than what were specified in the load or store instructions, then the event counts those smaller memory transactions."
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},
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{
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"ArchStdEvent": "MEMORY_ERROR",
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"PublicDescription": "Counts any detected correctable or uncorrectable physical memory errors (ECC or parity) in protected CPUs RAMs. On the core, this event counts errors in the caches (including data and tag rams). Any detected memory error (from either a speculative and abandoned access, or an architecturally executed access) is counted. Note that errors are only detected when the actual protected memory is accessed by an operation."
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},
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{
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"ArchStdEvent": "REMOTE_ACCESS",
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"PublicDescription": "Counts accesses to another chip, which is implemented as a different CMN mesh in the system. If the CHI bus response back to the core indicates that the data source is from another chip (mesh), then the counter is updated. If no data is returned, even if the system snoops another chip/mesh, then the counter is not updated."
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},
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{
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"ArchStdEvent": "MEM_ACCESS_RD",
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"PublicDescription": "Counts memory accesses issued by the CPU due to load operations. The event counts any memory load access, no matter whether the data is received from any level of cache hierarchy or external memory. The event also counts atomic load operations. If memory accesses are broken up by the load/store unit into smaller transactions that are issued by the bus interface, then the event counts those smaller transactions."
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},
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{
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"ArchStdEvent": "MEM_ACCESS_WR",
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"PublicDescription": "Counts memory accesses issued by the CPU due to store operations. The event counts any memory store access, no matter whether the data is located in any level of cache or external memory. The event also counts atomic load and store operations. If memory accesses are broken up by the load/store unit into smaller transactions that are issued by the bus interface, then the event counts those smaller transactions."
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},
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{
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"ArchStdEvent": "LDST_ALIGN_LAT",
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"PublicDescription": "Counts the number of memory read and write accesses in a cycle that incurred additional latency, due to the alignment of the address and the size of data being accessed, which results in store crossing a single cache line."
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},
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{
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"ArchStdEvent": "LD_ALIGN_LAT",
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"PublicDescription": "Counts the number of memory read accesses in a cycle that incurred additional latency, due to the alignment of the address and size of data being accessed, which results in load crossing a single cache line."
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},
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{
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"ArchStdEvent": "ST_ALIGN_LAT",
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"PublicDescription": "Counts the number of memory write access in a cycle that incurred additional latency, due to the alignment of the address and size of data being accessed incurred additional latency."
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},
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{
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"ArchStdEvent": "MEM_ACCESS_CHECKED",
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"PublicDescription": "Counts the number of memory read and write accesses in a cycle that are tag checked by the Memory Tagging Extension (MTE)."
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},
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{
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"ArchStdEvent": "MEM_ACCESS_CHECKED_RD",
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"PublicDescription": "Counts the number of memory read accesses in a cycle that are tag checked by the Memory Tagging Extension (MTE)."
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},
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{
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"ArchStdEvent": "MEM_ACCESS_CHECKED_WR",
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"PublicDescription": "Counts the number of memory write accesses in a cycle that is tag checked by the Memory Tagging Extension (MTE)."
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}
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]
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