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https://kernel.googlesource.com/pub/scm/linux/kernel/git/stable/linux-stable.git
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a3165abaa9
The S5M8763 MFD has no device tree compatible, and since board file support for it was removed, there's no way to use this MFD. After removing the remaining code for it from the MFD driver, also remove support for it in the s5m RTC driver, and all remaining references to it. Signed-off-by: David Virag <virag.david003@gmail.com> Acked-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Lee Jones <lee@kernel.org> Link: https://lore.kernel.org/r/20230131183008.4451-3-virag.david003@gmail.com
198 lines
4.4 KiB
C
198 lines
4.4 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (c) 2012 Samsung Electronics Co., Ltd
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* http://www.samsung.com
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*/
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#ifndef __LINUX_MFD_SEC_IRQ_H
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#define __LINUX_MFD_SEC_IRQ_H
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enum s2mpa01_irq {
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S2MPA01_IRQ_PWRONF,
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S2MPA01_IRQ_PWRONR,
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S2MPA01_IRQ_JIGONBF,
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S2MPA01_IRQ_JIGONBR,
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S2MPA01_IRQ_ACOKBF,
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S2MPA01_IRQ_ACOKBR,
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S2MPA01_IRQ_PWRON1S,
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S2MPA01_IRQ_MRB,
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S2MPA01_IRQ_RTC60S,
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S2MPA01_IRQ_RTCA1,
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S2MPA01_IRQ_RTCA0,
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S2MPA01_IRQ_SMPL,
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S2MPA01_IRQ_RTC1S,
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S2MPA01_IRQ_WTSR,
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S2MPA01_IRQ_INT120C,
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S2MPA01_IRQ_INT140C,
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S2MPA01_IRQ_LDO3_TSD,
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S2MPA01_IRQ_B16_TSD,
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S2MPA01_IRQ_B24_TSD,
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S2MPA01_IRQ_B35_TSD,
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S2MPA01_IRQ_NR,
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};
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#define S2MPA01_IRQ_PWRONF_MASK (1 << 0)
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#define S2MPA01_IRQ_PWRONR_MASK (1 << 1)
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#define S2MPA01_IRQ_JIGONBF_MASK (1 << 2)
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#define S2MPA01_IRQ_JIGONBR_MASK (1 << 3)
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#define S2MPA01_IRQ_ACOKBF_MASK (1 << 4)
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#define S2MPA01_IRQ_ACOKBR_MASK (1 << 5)
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#define S2MPA01_IRQ_PWRON1S_MASK (1 << 6)
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#define S2MPA01_IRQ_MRB_MASK (1 << 7)
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#define S2MPA01_IRQ_RTC60S_MASK (1 << 0)
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#define S2MPA01_IRQ_RTCA1_MASK (1 << 1)
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#define S2MPA01_IRQ_RTCA0_MASK (1 << 2)
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#define S2MPA01_IRQ_SMPL_MASK (1 << 3)
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#define S2MPA01_IRQ_RTC1S_MASK (1 << 4)
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#define S2MPA01_IRQ_WTSR_MASK (1 << 5)
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#define S2MPA01_IRQ_INT120C_MASK (1 << 0)
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#define S2MPA01_IRQ_INT140C_MASK (1 << 1)
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#define S2MPA01_IRQ_LDO3_TSD_MASK (1 << 2)
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#define S2MPA01_IRQ_B16_TSD_MASK (1 << 3)
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#define S2MPA01_IRQ_B24_TSD_MASK (1 << 4)
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#define S2MPA01_IRQ_B35_TSD_MASK (1 << 5)
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enum s2mps11_irq {
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S2MPS11_IRQ_PWRONF,
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S2MPS11_IRQ_PWRONR,
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S2MPS11_IRQ_JIGONBF,
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S2MPS11_IRQ_JIGONBR,
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S2MPS11_IRQ_ACOKBF,
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S2MPS11_IRQ_ACOKBR,
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S2MPS11_IRQ_PWRON1S,
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S2MPS11_IRQ_MRB,
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S2MPS11_IRQ_RTC60S,
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S2MPS11_IRQ_RTCA1,
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S2MPS11_IRQ_RTCA0,
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S2MPS11_IRQ_SMPL,
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S2MPS11_IRQ_RTC1S,
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S2MPS11_IRQ_WTSR,
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S2MPS11_IRQ_INT120C,
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S2MPS11_IRQ_INT140C,
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S2MPS11_IRQ_NR,
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};
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#define S2MPS11_IRQ_PWRONF_MASK (1 << 0)
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#define S2MPS11_IRQ_PWRONR_MASK (1 << 1)
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#define S2MPS11_IRQ_JIGONBF_MASK (1 << 2)
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#define S2MPS11_IRQ_JIGONBR_MASK (1 << 3)
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#define S2MPS11_IRQ_ACOKBF_MASK (1 << 4)
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#define S2MPS11_IRQ_ACOKBR_MASK (1 << 5)
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#define S2MPS11_IRQ_PWRON1S_MASK (1 << 6)
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#define S2MPS11_IRQ_MRB_MASK (1 << 7)
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#define S2MPS11_IRQ_RTC60S_MASK (1 << 0)
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#define S2MPS11_IRQ_RTCA1_MASK (1 << 1)
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#define S2MPS11_IRQ_RTCA0_MASK (1 << 2)
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#define S2MPS11_IRQ_SMPL_MASK (1 << 3)
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#define S2MPS11_IRQ_RTC1S_MASK (1 << 4)
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#define S2MPS11_IRQ_WTSR_MASK (1 << 5)
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#define S2MPS11_IRQ_INT120C_MASK (1 << 0)
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#define S2MPS11_IRQ_INT140C_MASK (1 << 1)
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enum s2mps14_irq {
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S2MPS14_IRQ_PWRONF,
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S2MPS14_IRQ_PWRONR,
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S2MPS14_IRQ_JIGONBF,
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S2MPS14_IRQ_JIGONBR,
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S2MPS14_IRQ_ACOKBF,
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S2MPS14_IRQ_ACOKBR,
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S2MPS14_IRQ_PWRON1S,
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S2MPS14_IRQ_MRB,
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S2MPS14_IRQ_RTC60S,
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S2MPS14_IRQ_RTCA1,
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S2MPS14_IRQ_RTCA0,
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S2MPS14_IRQ_SMPL,
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S2MPS14_IRQ_RTC1S,
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S2MPS14_IRQ_WTSR,
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S2MPS14_IRQ_INT120C,
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S2MPS14_IRQ_INT140C,
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S2MPS14_IRQ_TSD,
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S2MPS14_IRQ_NR,
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};
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enum s2mpu02_irq {
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S2MPU02_IRQ_PWRONF,
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S2MPU02_IRQ_PWRONR,
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S2MPU02_IRQ_JIGONBF,
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S2MPU02_IRQ_JIGONBR,
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S2MPU02_IRQ_ACOKBF,
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S2MPU02_IRQ_ACOKBR,
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S2MPU02_IRQ_PWRON1S,
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S2MPU02_IRQ_MRB,
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S2MPU02_IRQ_RTC60S,
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S2MPU02_IRQ_RTCA1,
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S2MPU02_IRQ_RTCA0,
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S2MPU02_IRQ_SMPL,
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S2MPU02_IRQ_RTC1S,
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S2MPU02_IRQ_WTSR,
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S2MPU02_IRQ_INT120C,
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S2MPU02_IRQ_INT140C,
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S2MPU02_IRQ_TSD,
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S2MPU02_IRQ_NR,
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};
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/* Masks for interrupts are the same as in s2mps11 */
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#define S2MPS14_IRQ_TSD_MASK (1 << 2)
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enum s5m8767_irq {
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S5M8767_IRQ_PWRR,
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S5M8767_IRQ_PWRF,
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S5M8767_IRQ_PWR1S,
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S5M8767_IRQ_JIGR,
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S5M8767_IRQ_JIGF,
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S5M8767_IRQ_LOWBAT2,
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S5M8767_IRQ_LOWBAT1,
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S5M8767_IRQ_MRB,
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S5M8767_IRQ_DVSOK2,
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S5M8767_IRQ_DVSOK3,
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S5M8767_IRQ_DVSOK4,
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S5M8767_IRQ_RTC60S,
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S5M8767_IRQ_RTCA1,
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S5M8767_IRQ_RTCA2,
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S5M8767_IRQ_SMPL,
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S5M8767_IRQ_RTC1S,
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S5M8767_IRQ_WTSR,
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S5M8767_IRQ_NR,
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};
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#define S5M8767_IRQ_PWRR_MASK (1 << 0)
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#define S5M8767_IRQ_PWRF_MASK (1 << 1)
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#define S5M8767_IRQ_PWR1S_MASK (1 << 3)
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#define S5M8767_IRQ_JIGR_MASK (1 << 4)
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#define S5M8767_IRQ_JIGF_MASK (1 << 5)
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#define S5M8767_IRQ_LOWBAT2_MASK (1 << 6)
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#define S5M8767_IRQ_LOWBAT1_MASK (1 << 7)
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#define S5M8767_IRQ_MRB_MASK (1 << 2)
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#define S5M8767_IRQ_DVSOK2_MASK (1 << 3)
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#define S5M8767_IRQ_DVSOK3_MASK (1 << 4)
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#define S5M8767_IRQ_DVSOK4_MASK (1 << 5)
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#define S5M8767_IRQ_RTC60S_MASK (1 << 0)
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#define S5M8767_IRQ_RTCA1_MASK (1 << 1)
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#define S5M8767_IRQ_RTCA2_MASK (1 << 2)
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#define S5M8767_IRQ_SMPL_MASK (1 << 3)
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#define S5M8767_IRQ_RTC1S_MASK (1 << 4)
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#define S5M8767_IRQ_WTSR_MASK (1 << 5)
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#endif /* __LINUX_MFD_SEC_IRQ_H */
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