Taniya Das ffe9232693 clk: qcom: gdsc: Set retain_ff before moving to HW CTRL ... [ Upstream commit 25708f73ff ] Enable the retain_ff_enable bit of GDSCR only if the GDSC is already ON. Once the GDSCR moves to HW control, SW no longer can determine the state of the GDSCR and setting the retain_ff bit could destroy all the register contents we intended to save. Therefore, move the retain_ff configuration before switching the GDSC to HW trigger mode. Cc: stable@vger.kernel.org Fixes: 173722995c ("clk: qcom: gdsc: Add support to enable retention of GSDCR") Signed-off-by: Taniya Das <quic_tdas@quicinc.com> Reviewed-by: Imran Shaik <quic_imrashai@quicinc.com> Tested-by: Imran Shaik <quic_imrashai@quicinc.com> # on QCS8300 Link: https://lore.kernel.org/r/20250214-gdsc_fixes-v1-1-73e56d68a80f@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org> [ Changed error path ] Signed-off-by: Sasha Levin <sashal@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>		2025-09-09 18:50:25 +02:00
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actions
analogbits	clk: analogbits: Fix incorrect calculation of vco rate delta	2025-03-13 12:49:58 +01:00
at91
axis
axs10x
baikal-t1
bcm	clk: bcm: rpi: Add NULL check in raspberrypi_clk_register()	2025-06-27 11:05:13 +01:00
berlin
davinci	clk: davinci: Add NULL check in davinci_lpsc_clk_register()	2025-08-28 16:24:09 +02:00
h8300
hisilicon
imgtec
imx	clk: imx8mp: inform CCF of maximum frequency of clocks	2025-06-04 14:37:59 +02:00
ingenic
keystone
loongson1
mediatek
meson	clk: meson-g12a: add missing fclk_div2 to spicc	2025-06-27 11:05:26 +01:00
microchip
mmp
mstar
mvebu
mxs
nxp
pistachio
pxa
qcom	clk: qcom: gdsc: Set retain_ff before moving to HW CTRL	2025-09-09 18:50:25 +02:00
ralink
renesas
rockchip	clk: rockchip: rk3036: mark ddrphy as critical	2025-06-27 11:05:32 +01:00
samsung	clk: samsung: Fix UBSAN panic in samsung_clk_init()	2025-04-10 14:31:59 +02:00
sifive
socfpga
spear
sprd
st
sunxi
sunxi-ng	clk: sunxi-ng: v3s: Fix de clock definition	2025-08-28 16:24:10 +02:00
tegra
ti	clk: ti: am43xx: Add clkctrl data for am43xx ADC1	2025-07-10 15:57:35 +02:00
uniphier
ux500
versatile
x86
xilinx	clk: xilinx: vcu: unregister pll_post only if registered correctly	2025-08-28 16:24:09 +02:00
zynq
zynqmp	Revert "drivers: clk: zynqmp: update divider round rate logic"	2024-12-14 19:51:12 +01:00
clk-asm9260.c
clk-aspeed.c
clk-aspeed.h
clk-ast2600.c
clk-axi-clkgen.c	clk: clk-axi-clkgen: fix fpfd_max frequency for zynq	2025-08-28 16:24:09 +02:00
clk-axm5516.c
clk-bd718x7.c
clk-bm1880.c
clk-bulk.c
clk-cdce706.c
clk-cdce925.c
clk-clps711x.c
clk-composite.c
clk-conf.c
clk-cs2000-cp.c
clk-devres.c
clk-divider.c
clk-fixed-factor.c
clk-fixed-mmio.c
clk-fixed-rate.c
clk-fractional-divider.c
clk-fractional-divider.h
clk-fsl-flexspi.c
clk-fsl-sai.c
clk-gate.c
clk-gemini.c
clk-gpio.c
clk-hi655x.c
clk-highbank.c
clk-hsdk-pll.c
clk-k210.c
clk-lmk04832.c
clk-lochnagar.c
clk-max9485.c
clk-max77686.c
clk-milbeaut.c
clk-moxart.c
clk-multiplier.c
clk-mux.c
clk-nomadik.c
clk-npcm7xx.c
clk-nspire.c
clk-oxnas.c
clk-palmas.c
clk-plldig.c
clk-pwm.c
clk-qoriq.c
clk-rk808.c
clk-s2mps11.c
clk-scmi.c
clk-scpi.c
clk-si514.c
clk-si544.c
clk-si570.c
clk-si5341.c
clk-si5351.c
clk-si5351.h
clk-sparx5.c
clk-stm32f4.c
clk-stm32h7.c
clk-stm32mp1.c
clk-twl6040.c
clk-versaclock5.c
clk-vt8500.c
clk-wm831x.c
clk-xgene.c
clk.c	clk: check for disabled clock-provider in of_clk_get_hw_from_clkspec()	2025-05-02 07:44:34 +02:00
clk.h
clkdev.c
Kconfig
Makefile