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tcl/target: Add support for TI MSPM0
Add basic support for Texas Instruments MSPM0L, C and G family of Cortex-M0 based micro-controllers. Change-Id: If2b5b1eca001f74d501ede67ec621c7497548a85 Co-developed-by: Henry Nguyen <h-nguyen8@ti.com> Signed-off-by: Henry Nguyen <h-nguyen8@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-on: https://review.openocd.org/c/openocd/+/8385 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-by: zapb <dev@zapb.de>
This commit is contained in:
Nishanth Menon
Antonio Borneo
parent
8a6f89ca17
commit
c81cb4aa2d
@ -7438,6 +7438,7 @@ flash bank $_FLASHNAME mspm0 0 0 0 0 $_TARGETNAME
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halt
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flash erase_sector 0 0 last
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flash write_image MAIN.bin 0x0
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mspm0_board_reset
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@end example
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@item @b{To erase and program the NONMAIN region:}
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@ -7445,10 +7446,29 @@ flash write_image MAIN.bin 0x0
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halt
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flash erase_sector 1 0 last
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flash write_image NONMAIN.bin 0x41C00000
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mspm0_board_reset
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@end example
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@end itemize
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@deffn {TCL proc} {mspm0_board_reset}
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Performs an nRST toggle on the device.
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@end deffn
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@deffn {TCL proc} {mspm0_mass_erase}
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Sends the mass erase command to the SEC-AP mailbox and then performs
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an nRST toggle. Once the command has been fully processed by the ROM,
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all MAIN memory will be erased. NOTE: This command is not supported
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on MSPM0C* family of devices.
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@end deffn
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@deffn {TCL proc} {mspm0_factory_reset}
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Sends the factory reset command to the SEC-AP mailbox and then performs
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an nRST toggle. Once the command has been fully processed by the ROM,
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all MAIN memory will be erased and NONMAIN will be reset to its default
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values.
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@end deffn
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@end deffn
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@deffn {Flash Driver} {niietcm4}
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199
tcl/target/ti_mspm0.cfg
Normal file
199
tcl/target/ti_mspm0.cfg
Normal file
@ -0,0 +1,199 @@
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# SPDX-License-Identifier: GPL-2.0-or-later
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# Copyright (C) 2023-2025 Texas Instruments Incorporated - https://www.ti.com/
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#
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# Texas Instruments MSPM0L/G - ARM Cortex-M0 @ 32MHz
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# https://www.ti.com/microcontrollers-mcus-processors/arm-based-microcontrollers/arm-cortex-m0-mcus/overview.html
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#
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source [find bitsbytes.tcl]
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if { [info exists CHIPNAME] } {
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set _CHIPNAME $CHIPNAME
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} else {
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# Meant to work with MSPM0L and MSPM0G class of devices.
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set _CHIPNAME mspm0x
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}
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if { [info exists CPUTAPID] } {
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set _DAP_TAPID $CPUTAPID
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} else {
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set _DAP_TAPID 0x4ba00477
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}
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if { [info exists DAP_SWD_ID] } {
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set _DAP_SWD_ID $DAP_SWD_ID
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} else {
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set _DAP_SWD_ID 0x2ba01477
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}
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source [find target/swj-dp.tcl]
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# MSPM0 only supports swd, so set it here and save a line for custom boards
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transport select swd
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set _DAP_ID $_DAP_SWD_ID
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swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_DAP_ID
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dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
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set _TARGETNAME $_CHIPNAME.cpu
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target create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap
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if { [info exists WORKAREABASE] } {
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set _WORKAREABASE $WORKAREABASE
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} else {
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set _WORKAREABASE 0x20000000
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}
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if { [info exists WORKAREASIZE] } {
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set _WORKAREASIZE $WORKAREASIZE
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} else {
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# Smallest SRAM size is 1K SRAM.
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set _WORKAREASIZE 0x400
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}
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#
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# MSPM0 Debug SubSystem Mailbox (DSSM) Communication helpers
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#
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proc _mspm0_wait_for_dssm_response {command} {
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# Wait for SECAP::RCR rx_valid to be set
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set timeout 1000
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while { [expr { [$::_CHIPNAME.dap apreg 2 0xc] & 0x1}] != 0x1 } {
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sleep 1
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set timeout [expr {$timeout - 1}]
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if { $timeout == 0 } {
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set rcr [$::_CHIPNAME.dap apreg 2 0xc]
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return -code error [format "MSPM0 SECAP RCR=0x%08x timeout rx_valid" $rcr]
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}
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}
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# Read SECAP::RXD to clear the RX_VALID bit
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set rxd [$::_CHIPNAME.dap apreg 2 0x8]
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# Read SECAP::RCR
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set rcr [$::_CHIPNAME.dap apreg 2 0xc]
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# Check if we got successful response. This is denoted as:
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# 8 LSBits of $command should matchup with SECAP::RCR
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# and
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# SECAP::RXD should be 0x10003
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if { ([expr { $command & 0xff}] == $rcr) && ($rxd == 0x10003) } {
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return 0
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}
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# Provide some debug log for users to report back if CMD fails.
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return -code error [format "MSPM0 SECAP CMD FAIL! RXD: 0x%08X RCR: 0x%08X" $rxd $rcr]
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}
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proc _mspm0_dssm_command {command} {
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# SECAP::TCR = command
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$::_CHIPNAME.dap apreg 2 0x4 $command
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# SECAP::TDR = 0x0
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$::_CHIPNAME.dap apreg 2 0x0 0x0
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# Read SECAP::RCR and RXD to clear up any prev pending reads
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set rxd [$::_CHIPNAME.dap apreg 2 0x8]
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set rcr [$::_CHIPNAME.dap apreg 2 0xc]
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# Make sure everything is synced
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sleep 1000
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# Trigger nRST
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mspm0_board_reset
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# Wait for ROM to do it's magic and respond back
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set res [_mspm0_wait_for_dssm_response $command]
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if { $res } {
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return $res
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}
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# Paranoid.. make sure ROM does what it is meant to do
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# RX valid should have been cleared after the operation is
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# complete
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sleep 1000
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# Trigger nRST to get back to sane system
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mspm0_board_reset
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sleep 1000
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return 0
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}
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# NOTE: Password authentication scheme is NOT supported atm.
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# mspm0_factory_reset: Factory reset the board
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proc mspm0_factory_reset {} {
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set res [_mspm0_dssm_command 0x020a]
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if { $res } {
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echo "Factory Reset failed!"
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} else {
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echo "Factory reset success! Halting processor"
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# We need to halt the processor else the WDT fires!
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halt
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}
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return $res
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}
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add_help_text mspm0_factory_reset "Force Factory reset to recover 'bricked' board"
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# NOTE: Password authentication scheme is NOT supported atm.
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# mspm0_mass_erase: Mass erase flash
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proc mspm0_mass_erase {} {
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set res [_mspm0_dssm_command 0x020c]
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if { $res } {
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echo "Mass Erase failed!"
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} else {
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echo "Mass Erase success! Halting Processor"
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# We need to halt the processor else the WDT fires!
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halt
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}
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return $res
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}
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add_help_text mspm0_mass_erase "Mass erase flash"
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# mspm0_start_bootloader: Ask explicitly for bootloader startup
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proc mspm0_start_bootloader {} {
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set res [_mspm0_dssm_command 0x0108]
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if { $res } {
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echo "Start BL failed!"
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}
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return $res
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}
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add_help_text mspm0_start_bootloader "Ask explicitly for bootloader startup"
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# MSPM0 requires board level NRST reset to be toggled for
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# Factory reset operations to function.
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# However this cannot be the default configuration as this
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# prevents reset init reset halt to function properly
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# since the Debug Subsystem (debugss) logic or coresight
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# seems impacted by nRST.
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# This can be overridden in board file as required.
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#
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# mspm0_board_reset: Board level reset
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proc mspm0_board_reset {} {
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set user_reset_config [reset_config]
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reset_config srst_only
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set errno [catch {reset}]
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eval reset_config $user_reset_config
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if {$errno} {error}
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}
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add_help_text mspm0_board_reset "Request a board level reset"
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# If the flash is empty or the device is already in low-power state, then
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# debug access is not available. to handle this, explicitly control power ap
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# to provide access. Refer to Technical Reference Manual for further info.
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proc _mspm0_enable_low_power_mode { } {
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# PWR_AP::DPREC <= FRCACT(3)=1, RST_CTL(14:16)=1, IHIB_SLP(20)=1
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$::_CHIPNAME.dap apreg 4 0x00 0x104008
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# PWR_AP::SPREC <= SYSRST=1
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$::_CHIPNAME.dap apreg 4 0xF0 0x01
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# PWR_AP::DPREC <= FRCACT(3)=1, IHIB_SLP(20)=1
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$::_CHIPNAME.dap apreg 4 0x00 0x100008
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}
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$_TARGETNAME configure -event examine-start { _mspm0_enable_low_power_mode }
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$_TARGETNAME configure -work-area-phys $_WORKAREABASE -work-area-size $_WORKAREASIZE -work-area-backup 0
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set _FLASHNAME $_CHIPNAME.flash
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flash bank $_FLASHNAME.main mspm0 0 0 0 0 $_TARGETNAME
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flash bank $_FLASHNAME.nonmain mspm0 0x41c00000 0 0 0 $_TARGETNAME
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flash bank $_FLASHNAME.data mspm0 0x41d00000 0 0 0 $_TARGETNAME
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cortex_m reset_config sysresetreq
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