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git://git.code.sf.net/p/openocd/code
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If watchdog is enabled, there's no way we can disable it while the flashing firmware is running. (Halt disables it, but software reset doesn't.) So let's have the flashing firmware refresh the watchdog regularly, in case it has been enabled by previously running software. Failure to do so could lead to a watchdog reset in the middle of the chip bieng programmed. Change-Id: I79d41593948aae0080480e891552e1c2ee3ccbd0 Signed-off-by: Aurélien Martin <martaurel@gmail.com> Reviewed-on: http://openocd.zylin.com/5266 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
59 lines
1.9 KiB
ArmAsm
59 lines
1.9 KiB
ArmAsm
/***************************************************************************
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* Copyright (C) 2014 Angus Gratton *
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* gus@projectgus.com *
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* *
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* This program is free software; you can redistribute it and/or modify *
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* it under the terms of the GNU General Public License as published by *
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* the Free Software Foundation; either version 2 of the License, or *
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* (at your option) any later version. *
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* *
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* This program is distributed in the hope that it will be useful, *
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* but WITHOUT ANY WARRANTY; without even the implied warranty of *
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
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* GNU General Public License for more details. *
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* *
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* You should have received a copy of the GNU General Public License *
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* along with this program; if not, write to the *
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* Free Software Foundation, Inc. *
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***************************************************************************/
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.text
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.syntax unified
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.thumb
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/*
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* Params :
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* r0 = byte count
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* r1 = buffer start
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* r2 = buffer end
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* r3 = target address
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* r6 = watchdog refresh value
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* r7 = watchdog refresh register address
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*/
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.thumb_func
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.global _start
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_start:
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wait_fifo:
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str r6, [r7, #0]
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ldr r5, [r1, #0]
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cmp r5, #0
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beq.n exit
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ldr r4, [r1, #4]
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cmp r4, r5
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beq.n wait_fifo
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ldmia r4!, {r5}
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stmia r3!, {r5}
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cmp r4, r2
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bcc.n no_wrap
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mov r4, r1
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adds r4, #8
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no_wrap:
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str r4, [r1, #4]
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subs r0, #4
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bne.n wait_fifo
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exit:
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bkpt #0x00
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.pool
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