stuartl/atinysynth
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ports/attiny85: Remove debugging #if blocks

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This commit is contained in:
Stuart Longland 2017-04-09 09:17:04 +10:00
parent b1ddd0c099
commit 3f7c6353c1
Signed by: stuartl
GPG Key ID: F954BBBB7948D546
1 changed files with 5 additions and 65 deletions
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64
ports/attiny85/main.c
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@ -28,32 +28,16 @@
#define SAMPLE_LEN 128 #define SAMPLE_LEN 128
static volatile uint8_t sample_buffer[SAMPLE_LEN]; static volatile uint8_t sample_buffer[SAMPLE_LEN];
static struct fifo_t sample_fifo; static struct fifo_t sample_fifo;
volatile uint8_t underflow = 0;
struct voice_ch_t poly_voice[16]; struct voice_ch_t poly_voice[16];
struct poly_synth_t synth; struct poly_synth_t synth;
int main(void) { int main(void) {
#if 0
/* Turn clock speed right up */
CLKPR = (1 << CLKPCE);
/* Turn on all except ADC */
PRR = (1 << PRADC);
/* Start up PLL */
PLLCSR = (1 << PLLE);
while (!(PLLCSR & (1<<PLOCK)));
PLLCSR |= (1<<PCKE);
#endif
#if 1
fifo_init(&sample_fifo, sample_buffer, SAMPLE_LEN); fifo_init(&sample_fifo, sample_buffer, SAMPLE_LEN);
memset(poly_voice, 0, sizeof(poly_voice)); memset(poly_voice, 0, sizeof(poly_voice));
synth.voice = poly_voice; synth.voice = poly_voice;
synth.enable = 0; synth.enable = 0;
synth.mute = 0; synth.mute = 0;
#endif
/* Enable output on PB4 (PWM out) */ /* Enable output on PB4 (PWM out) */
DDRB |= (1 << 4) | (1 << 3); DDRB |= (1 << 4) | (1 << 3);
@ -73,68 +57,24 @@ int main(void) {
OCR0A = (uint8_t)((uint32_t)F_CPU / (8*(uint32_t)SYNTH_FREQ)); OCR0A = (uint8_t)((uint32_t)F_CPU / (8*(uint32_t)SYNTH_FREQ));
TIMSK |= (1 << OCIE0A); /* Enable interrupts */ TIMSK |= (1 << OCIE0A); /* Enable interrupts */
#if 1
/* Configure the synthesizer */ /* Configure the synthesizer */
synth.enable = 1; synth.enable = 1;
voice_wf_set_square(&poly_voice[0].wf, 1000, 127); voice_wf_set_square(&poly_voice[0].wf, 1000, 127);
poly_voice[0].adsr.time_scale = 32; poly_voice[0].adsr.time_scale = 32;
poly_voice[0].adsr.sustain_time = 120; poly_voice[0].adsr.sustain_time = 120;
poly_voice[0].adsr.sustain_amp = 255; poly_voice[0].adsr.sustain_amp = 255;
#endif
#if 1
sei(); sei();
while(1) { while(1) {
#if 1
while (sample_fifo.stored_sz < SAMPLE_LEN) {
int16_t s = poly_synth_next(&synth);
fifo_write_one(&sample_fifo,
128 + (s >> 9));
#if 1
PORTB ^= (1 << 3);
#endif
if (poly_voice[0].adsr.state == if (poly_voice[0].adsr.state ==
ADSR_STATE_DONE) ADSR_STATE_DONE)
adsr_reset(&poly_voice[0].adsr); adsr_reset(&poly_voice[0].adsr);
while(underflow);
} }
#if 0
poly_evt.flags = POLY_EVT_TYPE_IFREQ;
poly_evt.value += 100;
if (poly_evt.value > 2000)
poly_evt.value = 100;
poly_load(&poly_evt);
#endif
#endif
}
#else
while (1) {
int i;
for (i = 0; i < 255; i++) {
OCR1B = i;
_delay_us(100);
}
for (i = 255; i > 0; i--) {
OCR1B = i;
_delay_us(100);
}
PORTB ^= (1 << 3);
}
#endif
return 0; return 0;
} }
ISR(TIM0_COMPA_vect) { ISR(TIM0_COMPA_vect) {
#if 1 int8_t s = poly_synth_next(&synth);
uint8_t sample = fifo_read_one(&sample_fifo); OCR1B = s + 128;
if (sample >= 0) {
OCR1B = sample;
} else {
OCR1B = 128;
underflow = 1;
}
#else
PORTB ^= (1 << 3); PORTB ^= (1 << 3);
#endif
} }